2011/6/28 Martin Kielhorn <[email protected]>: > 2011/6/28 Mark Marshall <[email protected]>: >> On 28/06/2011 13:45, Martin Kielhorn wrote: >>> >>> 2011/6/28 Timothy Normand Miller<[email protected]>: >>>> >>>> The reference might be wrong. We've had two different ones. >> >> I think Tim's correct. The board has two xtal's on it, one connected to the >> XP10 and the other to the S3. The S3 clock is the 133 MHz, this has never >> really changed (as far as I know). The XP10 clock has been either 125MHz or >> 156.25 MHz (5/4 * 125). (the XP10 clock gets fed into the S3, and it's the >> S3 that generates the video timing). >> > I'll look at the hardware the next time I open the system. > For now I solved the problem by supplying different clock divider settings. > ([sel=1 pre=28 post=1] instead of [sel=1 pre=35 post=1])
I compiled the code as a standalone program and it works fine. http://paste.lisp.org/+2MWR Maybe it is some bug because I compiled the oga1-vid-test on a Debian 6 and run it on Debian 5. It returns sel=1 pre=28 post=1 Or encoded into the register value: 737 As opposed to 1 35 1. -- Martin Kielhorn _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
