Hi, I have a problem in the sense that the 1280x1024-32@60Hz mode isn't really 60Hz. The screen says the VSYNC rate is 47Hz. The Samsung screen actually displays the test picture, but the ForthDD display that I need to get running, doesn't work.
Hopefully someone on this list can shed some light on this. I uploaded two screenshots of a tool that came with the ForthDD display http://imgur.com/a/a4f6p The top one is with the Nvidia card and the bottom one with the open graphics hardware. The OGD1 tool prints this: Requested clock = 216180000 Actual clock = 214285680 (difference = 1894320) That means the actual clock is 0.8% off, that doesn't explain the 47Hz VSYNC rate that the screens report Appart from the frequencies I see differences in the IFM_PIX_SYS_RATIO and the tick at 'h+ sync'. This is the output of oga1-vide-test: cyberpower:/opt/ogp/bin# ./oga1-vid-test --busid 0b:1.0 oga1_i2c_get_edid: Reading EDID for top head. manufacturer ID = "FDD" product=4868 sn=16777216 (2002 week 16) EDID version 1.3 Display is digital Digital interface: DVI Color Bit Depth is undefined image size 32x24 display gama 1.000000 Power management: Color encoding : RGB 4:4:4:4 & YCrCb 4:4:4 Features: (default GTF supported) Chromaticity Coordinates: Red: 280:15c 0.625000:0.339844 Green: 129:26c 0.290039:0.605469 Blue: 09a:048 0.150391:0.070312 White: 122:130 0.283203:0.296875 Established Timings: Standard Timing: 0: 1280x1024 @ 60 Hz 1: 1280x1024 @ 75 Hz 2: 1280x1024 @ 85 Hz 3: 1024x768 @ 85 Hz Descriptor 0: pixel clock = 108090 KHz H active 1280 H blanking 408 V active 1024 V blanking 42 H sync offset 48 H sync width 112 V sync offset 1 V sync width 3 H image size 320mm V image size 240mm H border 0 V border 0 flags 1e Descriptor 1: (FF) Serial Number ;=?A Descriptor 2: (FE) ASCII string SXGA I/F Descriptor 3: (FE) ASCII string SXGA 00 ff ff ff ff ff ff 00 18 84 04 13 00 00 00 01 0c 10 01 03 81 20 18 00 09 04 88 a0 57 4a 9b 26 WJ & 12 48 4c 00 00 00 81 80 81 8f 81 99 61 59 01 01 HL aY 01 01 01 01 01 01 39 2a 00 98 51 00 2a 40 30 70 9* Q *@0p 13 00 40 f0 10 00 00 1e 00 00 00 ff 00 3b 3d 3f @ ;=? 41 0b 0a 0a 0a 0a 0a 0a 0a 0a 00 00 00 fe 00 53 A S 58 47 41 20 49 2f 46 0a 20 20 20 20 00 00 00 fe XGA I/F 00 53 58 47 41 0a 20 20 20 20 20 20 20 20 00 62 SXGA b oga1_i2c_get_edid: Reading EDID for bottom head. oga1_i2c_get_edid: failed to read byte 0. Looking for mode: ddc Requested clock = 216180000 Actual clock = 214285680 (difference = 1894320) Dividers = sel:1 pre:35 post:1 Setting Up DVI on top head. oga1_dvi_init_single_link: pixel clock = 108090000 Loading Video Program on top head (1280x1024@60). start=0x8000000 pitch=1280 hres=1280, hfp=48, hsync=112, hbp=248 [408] vres=1024, vfp=1, vsync=3, vbp=38 [42] pix-clock=108090000 digital hsync-low vsync-high oga1_set_video_mode: digital 1 dvi_sl 1 vid_mode 5 oga1_set_video_mode: pixel_info = d output_mode = 1 00987654 00123456 I checked that the nvidia tool reports exactly the same EDID information. -- Martin Kielhorn Randall Division of Cell & Molecular Biophysics King's College London, New Hunt's House Guy's Campus, London SE1 1UL, U.K. tel: +44 (0) 207 848 6519, fax: +44 (0) 207 848 6435
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