What we want is a circuit whose input is a register number and whose output is the register value. In the case of R0, the value is fixed at zero. We have two options to implement this:
1. Hack the SRAM so that R0's storage cells are replaced by fixed values. 2. Multiplex the output of the SRAM and substitute zero for the case where R0 is selected. Maybe there are other options, but you can't get away from the fact that you have an address that goes into some logic and you get some data out. The critical path through that circuit is, at a very minimum, the same as for any other register. There's no way to make it magically shorter for the zero register case. You have to set your clock period to be greater than the delay through the longest path. On Fri, Mar 22, 2013 at 7:50 PM, Peter Stuge <[email protected]> wrote: > Timothy Normand Miller wrote: > > No. What if you select a different register? At _best_ (assume we can > > hack the internals of an SRAM block), it has the same circuit delay as > > accessing any other register. > > The optimization would be to have a special, shorter, circuit that > detects R0 and outputs the fixed value. If SRAM is slower than logic > the longer circuit for all non-R0 register accesses might be worth it? > > If the two extra gates (detector OR, output AND) have too much impact > on non-R0 register accesses then it certainly isn't worth it. > > > //Peter > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/ Open Graphics Project
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