Moin,
On Sat, 21 Jul 2007 11:11:09 -0700
James Richard Tyrer <[EMAIL PROTECTED]> wrote:
> Dieter wrote:
> > If there is a lump of functionality that will take a lot of design time
> > but is available as an inexpensive and well documented chip, it might
> > make sense to use that chip.
>
> There are two competing factors here. To buy a chip obviously costs
> money and adding a 500+ connection chip to a board obviously will
> increase the board cost. OTOH, making a larger single chip isn't linear
> -- double the size and you more than double the cost, and double the
> size and interconnects require more than twice the space (so you have to
> more than double the chip size). So, it is an optimization problem.
Guessing from the schematics and the available real estate
on the FPGA i'd say that we are pin limited on TRV10. Which means
that additional logic doesn't come at any cost (beside longer
synthesis/verification time). And the cost of additional pins
depends highly on the used technology.
Board cost is defined by the number of layers it has and
the number of populated components. The package of the
components is also a factor, but with a BGA for TRV10
we are already at the most expensive point (if there
is one BGA, another doesn't add any more cost than being
an additional component).
What might (and IMHO will) be a problem is that the whole
logic might not fit on the FPGA anymore (verification).
And something not talked about is that we will have to pay
patent royalities for any video decoder chip (unless we can
prove that all related patents are void, but good luck with that).
This is currently for me the only reason for a two chip solution,
to avoid additional cost for people who do not want a video decoder.
> In this case, this chip appears to have a lot of features which would
> require extensive design work to equal.
Interfacing the chip isn't easy either.
> > There is also the Plan B approach of trying to find existing chips
> > that can do what we need without having to build our own ASIC.
>
> Yes, if we could make a system out of existing chips and programmable
> logic (CPLDs not FPGAs), it might be less expensive -- you have to
> consider the board costs. IIUC, CPLDs can be directly converted to
> ASICs without much trouble at least that was the case with regular
> (non-complex) PLDs.
Forget CPLDs. At the logic size we need, CPLDs are a lot more expensive
than FPGAs. And no, conversion of CPLDs to ASICs isn't easier than FPGAs.
Both require a rerun trough the synthesizer and a post layout timing
verification. But that's automagic these days anyways.
Attila Kinali
--
Linux ist... wenn man einfache Dinge auch mit einer kryptischen
post-fix Sprache loesen kann
-- Daniel Hottinger
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