The attached patch si_subset.diff enables the target SI generator to
work with ISA subsets. Previously I had not tested this case as no
one was using it, but it looks like it is useful as a way to avoid
having to explicitly list unsupported instructions in the set of dummy
instructions. There are also a few minor changes to fix compilation
warnings for si_gen.cxx. The generator still requires that you
provide SI for all instructions in the processor's target ISA subset.
The second patch, sl_example.diff, shows how to modify the definitions
of the SL target to use a second ISA subset. I do not plan to check
these changes in -- the patch is provided only as an example. Here, a
common subset of instructions is factored out to form the SL5 subset.
The instruction "smult" is added to the list of dummy instructions for
the other targets -- it seems to be an odd case where it is supported
by SL5 but not the other processors which otherwise support many more
instructions, and I think it seems reasonable to require that it be
listed as a dummy.
Could a gatekeeper please review the first patch? Thanks,
-David Coakley / AMD Open Source Compiler Engineering
Index: osprey/common/targ_info/generate/si_gen.cxx
===================================================================
--- osprey/common/targ_info/generate/si_gen.cxx (revision 3467)
+++ osprey/common/targ_info/generate/si_gen.cxx (working copy)
@@ -89,8 +89,8 @@
const int max_results = ISA_OPERAND_max_results;
const int max_machine_slots = 16;
-static ISA_SUBSET machine_isa;
static int current_machine_slot;
+static ISA_SUBSET machine_isa[max_machine_slots];
static std::string machine_name[max_machine_slots];
static const char * const interface[] = {
@@ -1172,7 +1172,7 @@
GNAME gname("latency");
output_latencies[*this] = gname;
- fprintf(fd,"static const mUINT8 %s[%d] = {",gname.Gname(),times.size());
+ fprintf(fd,"static const mUINT8 %s[%lu] = {",gname.Gname(),times.size());
bool is_first = true;
std::vector<int>::iterator i;
@@ -1696,7 +1696,7 @@
}
i = 1;
- fprintf(fd,"\nconst SI SI_all[%u] = {\n", instruction_group_set.size());
+ fprintf(fd,"\nconst SI SI_all[%lu] = {\n", instruction_group_set.size());
for (mi = instruction_group_set.begin();
mi != instruction_group_set.end();
++mi
@@ -1714,7 +1714,7 @@
{
std::list<INSTRUCTION_GROUP*>::iterator iig;
- fprintf(fd,"\nstatic const int SI_ID_si_%d[%d] = {",machine_slot,
+ fprintf(fd,"\nstatic const int SI_ID_si_%d[%lu] = {",machine_slot,
by_machine_instruction_groups[machine_slot].size());
bool is_first = true;
@@ -1733,7 +1733,7 @@
void INSTRUCTION_GROUP::Output_Members(FILE* fd, int machine_slot)
{
- fprintf(fd," %-20u /* SI_ID_count */,\n",
+ fprintf(fd," %-20lu /* SI_ID_count */,\n",
by_machine_instruction_groups[machine_slot].size());
fprintf(fd," SI_ID_si_%-11d /* SI_ID_si */,\n",machine_slot);
}
@@ -1780,6 +1780,9 @@
static std::vector<bool> top_sched_info_defined[max_machine_slots];
// Which elements defined
+
+ static INSTRUCTION_GROUP* machine_dummies[max_machine_slots];
+ // Pointer to dummy instruction used to fill unused slots
};
std::vector<INSTRUCTION_GROUP*>
@@ -1787,14 +1790,14 @@
std::vector<bool>
TOP_SCHED_INFO_MAP::top_sched_info_defined[max_machine_slots];
+INSTRUCTION_GROUP* TOP_SCHED_INFO_MAP::machine_dummies[max_machine_slots];
+
void TOP_SCHED_INFO_MAP::Create_Dummies( void )
{
INSTRUCTION_GROUP *dummies = NULL;
- TOP_SCHED_INFO_MAP::top_sched_info_ptr_map[current_machine_slot].resize(
- TOP_count,NULL);
- TOP_SCHED_INFO_MAP::top_sched_info_defined[current_machine_slot].resize(
- TOP_count,false);
+ top_sched_info_ptr_map[current_machine_slot].resize(TOP_count,NULL);
+ top_sched_info_defined[current_machine_slot].resize(TOP_count,false);
for ( int i = 0; i < TOP_count; ++i ) {
if ( TOP_is_dummy((TOP)i) ) {
@@ -1806,6 +1809,7 @@
top_sched_info_ptr_map[current_machine_slot][i] = dummies;
}
}
+ machine_dummies[current_machine_slot] = dummies;
}
void TOP_SCHED_INFO_MAP::Add_Entry( TOP top, INSTRUCTION_GROUP* ig )
@@ -1828,14 +1832,14 @@
bool err = false;
bool is_first = true;
for ( i = 0; i < TOP_count; ++i ) {
- bool isa_member = ISA_SUBSET_Member(machine_isa, (TOP)i);
+ bool isa_member = ISA_SUBSET_Member(machine_isa[machine_slot], (TOP)i);
bool is_dummy = TOP_is_dummy((TOP)i);
if ( top_sched_info_defined[machine_slot][i] ) {
if ( ! isa_member ) {
fprintf(stderr,
"### Warning: scheduling info for non-%s ISA opcode %s (%s)\n",
- ISA_SUBSET_Name(machine_isa),
+ ISA_SUBSET_Name(machine_isa[machine_slot]),
TOP_Name((TOP)i),
machine_name[machine_slot].c_str());
} else if ( is_dummy ) {
@@ -1858,8 +1862,13 @@
// If we have seen a fatal error, skip printing the entry to avoid a crash.
if ( ! err ) {
Maybe_Print_Comma(fd,is_first);
- fprintf(fd,"\n %-4u /* %s */",
- top_sched_info_ptr_map[machine_slot][i]->Id(),TOP_Name((TOP)i));
+ if ( ! isa_member )
+ fprintf(fd,"\n %-4u /* %s (dummy, not in ISA subset %s) */",
+ machine_dummies[machine_slot]->Id(),TOP_Name((TOP)i),
+ ISA_SUBSET_Name(machine_isa[machine_slot]));
+ else
+ fprintf(fd,"\n %-4u /* %s */",
+
top_sched_info_ptr_map[machine_slot][i]->Id(),TOP_Name((TOP)i));
}
}
fprintf(fd,"\n};\n");
@@ -1886,7 +1895,7 @@
void Machine( const char* name, ISA_SUBSET isa )
{
machine_name[current_machine_slot] = name;
- machine_isa = isa;
+ machine_isa[current_machine_slot] = isa;
TOP_SCHED_INFO_MAP::Create_Dummies();
}
Index: osprey/common/targ_info/proc/SL/sl5_si.cxx
===================================================================
--- osprey/common/targ_info/proc/SL/sl5_si.cxx (revision 3467)
+++ osprey/common/targ_info/proc/SL/sl5_si.cxx (working copy)
@@ -44,7 +44,7 @@
void Generate_SL5 (void)
{
- Machine("sl5", ISA_SUBSET_MIPS4);
+ Machine("sl5", ISA_SUBSET_SL5);
res_issue = RESOURCE_Create("issue", 1);
res_memory = RESOURCE_Create("memory", 1);
Index: osprey/common/targ_info/proc/SL/sl1_dsp_si.cxx
===================================================================
--- osprey/common/targ_info/proc/SL/sl1_dsp_si.cxx (revision 3467)
+++ osprey/common/targ_info/proc/SL/sl1_dsp_si.cxx (working copy)
@@ -1344,6 +1344,7 @@
Resource_Requirement(res_issue, 0);
Instruction_Group("dummy",
+ TOP_smult,
TOP_asm,
TOP_intrncall,
TOP_spadjust,
Index: osprey/common/targ_info/proc/SL/sl2_mcore_si.cxx
===================================================================
--- osprey/common/targ_info/proc/SL/sl2_mcore_si.cxx (revision 3467)
+++ osprey/common/targ_info/proc/SL/sl2_mcore_si.cxx (working copy)
@@ -1360,6 +1360,7 @@
Resource_Requirement(res_integer, 0);
Instruction_Group("dummy",
+ TOP_smult,
TOP_asm,
TOP_intrncall,
TOP_spadjust,
Index: osprey/common/targ_info/proc/SL/sl1_pcore_si.cxx
===================================================================
--- osprey/common/targ_info/proc/SL/sl1_pcore_si.cxx (revision 3467)
+++ osprey/common/targ_info/proc/SL/sl1_pcore_si.cxx (working copy)
@@ -1342,6 +1342,7 @@
Resource_Requirement(res_issue, 0);
Instruction_Group("dummy",
+ TOP_smult,
TOP_asm,
TOP_intrncall,
TOP_spadjust,
Index: osprey/common/targ_info/proc/SL/sl2_pcore_si.cxx
===================================================================
--- osprey/common/targ_info/proc/SL/sl2_pcore_si.cxx (revision 3467)
+++ osprey/common/targ_info/proc/SL/sl2_pcore_si.cxx (working copy)
@@ -1360,6 +1360,7 @@
Resource_Requirement(res_integer, 0);
Instruction_Group("dummy",
+ TOP_smult,
TOP_asm,
TOP_intrncall,
TOP_spadjust,
Index: osprey/common/targ_info/generate/si_gen.cxx
===================================================================
--- osprey/common/targ_info/generate/si_gen.cxx (revision 3467)
+++ osprey/common/targ_info/generate/si_gen.cxx (working copy)
@@ -89,8 +89,8 @@
const int max_results = ISA_OPERAND_max_results;
const int max_machine_slots = 16;
-static ISA_SUBSET machine_isa;
static int current_machine_slot;
+static ISA_SUBSET machine_isa[max_machine_slots];
static std::string machine_name[max_machine_slots];
static const char * const interface[] = {
@@ -1172,7 +1172,7 @@
GNAME gname("latency");
output_latencies[*this] = gname;
- fprintf(fd,"static const mUINT8 %s[%d] = {",gname.Gname(),times.size());
+ fprintf(fd,"static const mUINT8 %s[%lu] = {",gname.Gname(),times.size());
bool is_first = true;
std::vector<int>::iterator i;
@@ -1696,7 +1696,7 @@
}
i = 1;
- fprintf(fd,"\nconst SI SI_all[%u] = {\n", instruction_group_set.size());
+ fprintf(fd,"\nconst SI SI_all[%lu] = {\n", instruction_group_set.size());
for (mi = instruction_group_set.begin();
mi != instruction_group_set.end();
++mi
@@ -1714,7 +1714,7 @@
{
std::list<INSTRUCTION_GROUP*>::iterator iig;
- fprintf(fd,"\nstatic const int SI_ID_si_%d[%d] = {",machine_slot,
+ fprintf(fd,"\nstatic const int SI_ID_si_%d[%lu] = {",machine_slot,
by_machine_instruction_groups[machine_slot].size());
bool is_first = true;
@@ -1733,7 +1733,7 @@
void INSTRUCTION_GROUP::Output_Members(FILE* fd, int machine_slot)
{
- fprintf(fd," %-20u /* SI_ID_count */,\n",
+ fprintf(fd," %-20lu /* SI_ID_count */,\n",
by_machine_instruction_groups[machine_slot].size());
fprintf(fd," SI_ID_si_%-11d /* SI_ID_si */,\n",machine_slot);
}
@@ -1780,6 +1780,9 @@
static std::vector<bool> top_sched_info_defined[max_machine_slots];
// Which elements defined
+
+ static INSTRUCTION_GROUP* machine_dummies[max_machine_slots];
+ // Pointer to dummy instruction used to fill unused slots
};
std::vector<INSTRUCTION_GROUP*>
@@ -1787,14 +1790,14 @@
std::vector<bool>
TOP_SCHED_INFO_MAP::top_sched_info_defined[max_machine_slots];
+INSTRUCTION_GROUP* TOP_SCHED_INFO_MAP::machine_dummies[max_machine_slots];
+
void TOP_SCHED_INFO_MAP::Create_Dummies( void )
{
INSTRUCTION_GROUP *dummies = NULL;
- TOP_SCHED_INFO_MAP::top_sched_info_ptr_map[current_machine_slot].resize(
- TOP_count,NULL);
- TOP_SCHED_INFO_MAP::top_sched_info_defined[current_machine_slot].resize(
- TOP_count,false);
+ top_sched_info_ptr_map[current_machine_slot].resize(TOP_count,NULL);
+ top_sched_info_defined[current_machine_slot].resize(TOP_count,false);
for ( int i = 0; i < TOP_count; ++i ) {
if ( TOP_is_dummy((TOP)i) ) {
@@ -1806,6 +1809,7 @@
top_sched_info_ptr_map[current_machine_slot][i] = dummies;
}
}
+ machine_dummies[current_machine_slot] = dummies;
}
void TOP_SCHED_INFO_MAP::Add_Entry( TOP top, INSTRUCTION_GROUP* ig )
@@ -1828,14 +1832,14 @@
bool err = false;
bool is_first = true;
for ( i = 0; i < TOP_count; ++i ) {
- bool isa_member = ISA_SUBSET_Member(machine_isa, (TOP)i);
+ bool isa_member = ISA_SUBSET_Member(machine_isa[machine_slot], (TOP)i);
bool is_dummy = TOP_is_dummy((TOP)i);
if ( top_sched_info_defined[machine_slot][i] ) {
if ( ! isa_member ) {
fprintf(stderr,
"### Warning: scheduling info for non-%s ISA opcode %s (%s)\n",
- ISA_SUBSET_Name(machine_isa),
+ ISA_SUBSET_Name(machine_isa[machine_slot]),
TOP_Name((TOP)i),
machine_name[machine_slot].c_str());
} else if ( is_dummy ) {
@@ -1858,8 +1862,13 @@
// If we have seen a fatal error, skip printing the entry to avoid a crash.
if ( ! err ) {
Maybe_Print_Comma(fd,is_first);
- fprintf(fd,"\n %-4u /* %s */",
- top_sched_info_ptr_map[machine_slot][i]->Id(),TOP_Name((TOP)i));
+ if ( ! isa_member )
+ fprintf(fd,"\n %-4u /* %s (dummy, not in ISA subset %s) */",
+ machine_dummies[machine_slot]->Id(),TOP_Name((TOP)i),
+ ISA_SUBSET_Name(machine_isa[machine_slot]));
+ else
+ fprintf(fd,"\n %-4u /* %s */",
+
top_sched_info_ptr_map[machine_slot][i]->Id(),TOP_Name((TOP)i));
}
}
fprintf(fd,"\n};\n");
@@ -1886,7 +1895,7 @@
void Machine( const char* name, ISA_SUBSET isa )
{
machine_name[current_machine_slot] = name;
- machine_isa = isa;
+ machine_isa[current_machine_slot] = isa;
TOP_SCHED_INFO_MAP::Create_Dummies();
}
Index: osprey/common/targ_info/isa/SL/isa_subset.cxx
===================================================================
--- osprey/common/targ_info/isa/SL/isa_subset.cxx (revision 3467)
+++ osprey/common/targ_info/isa/SL/isa_subset.cxx (working copy)
@@ -33,53 +33,13 @@
main()
{
- ISA_SUBSET mips4;
+ ISA_SUBSET mips4, sl5;
ISA_Subset_Begin("MIPS");
- mips4 = ISA_Subset_Create(NULL,"MIPS4");
+ mips4 = ISA_Subset_Create(NULL, "MIPS4");
+
Instruction_Group(mips4,
-#if defined(TARG_SL)
- TOP_loop,
- TOP_mvtc,
- TOP_mvfc,
- TOP_mvtc_i,
- TOP_ret,
- TOP_abs16,
- TOP_add16,
- TOP_add16_i,
- TOP_add16_sp,
- TOP_and16,
- TOP_and16_i,
- TOP_jr16,
- TOP_jr16_lnk,
- TOP_ldw16,
- TOP_ldub16_rs,
- TOP_lduh16_rs,
- TOP_mv16,
- TOP_mv16_i,
- TOP_mvfc16,
- TOP_mvtc16,
- TOP_nop16,
- TOP_inv16,
- TOP_or16,
- TOP_or16_i,
- TOP_pop16,
- TOP_push16,
- TOP_ret16,
- TOP_shll16,
- TOP_shll16_i,
- TOP_shra16,
- TOP_shra16_i,
- TOP_shrl16,
- TOP_shrl16_i,
- TOP_stw16,
- TOP_sub16,
- TOP_sub16_i,
- TOP_xor16,
- TOP_xor16_i,
- TOP_br16_eqz,
- TOP_br16_nez,
//new c3
TOP_c3_aadda,
TOP_c3_bitr,
@@ -148,153 +108,17 @@
TOP_c3_mvtacc,
TOP_c3_mvtaddr,
TOP_c3_mvtadds,
-#endif
- TOP_lb,
- TOP_lbu,
- TOP_lh,
- TOP_lhu,
- TOP_lw,
- TOP_lwl,
- TOP_lwr,
- TOP_sb,
- TOP_sh,
- TOP_sw,
- TOP_swl,
- TOP_swr,
- TOP_ll,
- TOP_sc,
TOP_sync,
- TOP_lwu,
- TOP_ld,
- TOP_ldl,
- TOP_ldr,
- TOP_lld,
- TOP_sd,
- TOP_sdl,
- TOP_sdr,
- TOP_scd,
TOP_pref,
TOP_prefx,
- TOP_add,
- TOP_addi,
- TOP_addiu,
- TOP_addu,
TOP_div,
TOP_divu,
TOP_mult,
TOP_multu,
- TOP_slt,
- TOP_slti,
- TOP_sltiu,
- TOP_sltu,
- TOP_sub,
- TOP_subu,
- TOP_dadd,
- TOP_daddi,
- TOP_daddiu,
- TOP_daddu,
TOP_ddiv,
TOP_ddivu,
TOP_dmult,
TOP_dmultu,
- TOP_dsub,
- TOP_dsubu,
- TOP_and,
- TOP_andi,
- TOP_lui,
- TOP_nor,
- TOP_or,
- TOP_ori,
- TOP_xor,
- TOP_xori,
- TOP_mfhi,
- TOP_mflo,
- TOP_mthi,
- TOP_mtlo,
-#if defined(TARG_SL)
- TOP_smult,
- TOP_mc_abs,
- TOP_mc_zc_eq,
- TOP_mc_zc_ne,
- TOP_mc_zc_gt,
- TOP_mc_zc_ge,
- TOP_mc_zc_lt,
- TOP_mc_zc_le,
- TOP_mc_z_eq,
- TOP_mc_z_ne,
- TOP_mc_z_gt,
- TOP_mc_z_ge,
- TOP_mc_z_lt,
- TOP_mc_z_le,
- TOP_mc_zn_eq,
- TOP_mc_zn_ne,
- TOP_mc_zn_gt,
- TOP_mc_zn_ge,
- TOP_mc_zn_lt,
- TOP_mc_zn_le,
- TOP_mc_r_eq,
- TOP_mc_r_ne,
- TOP_mc_r_gt,
- TOP_mc_r_ge,
- TOP_mc_r_lt,
- TOP_mc_r_le,
- TOP_depb,
- TOP_extrbs,
- TOP_extrbu,
-#endif
- TOP_movf,
- TOP_movn,
- TOP_movt,
- TOP_movz,
- TOP_sll,
- TOP_sllv,
- TOP_sra,
- TOP_srav,
- TOP_srl,
- TOP_srlv,
- TOP_dsll,
- TOP_dsll32,
- TOP_dsllv,
- TOP_dsra,
- TOP_dsra32,
- TOP_dsrav,
- TOP_dsrl,
- TOP_dsrl32,
- TOP_dsrlv,
- TOP_beq,
- TOP_bgez,
- TOP_bgezal,
- TOP_bgtz,
- TOP_blez,
- TOP_bltz,
- TOP_bltzal,
- TOP_bne,
- TOP_j,
- TOP_jal,
- TOP_jalr,
- TOP_jr,
- TOP_break,
- TOP_syscall,
- TOP_teq,
- TOP_teqi,
- TOP_tge,
- TOP_tgei,
- TOP_tgeiu,
- TOP_tgeu,
- TOP_tlt,
- TOP_tlti,
- TOP_tltiu,
- TOP_tltu,
- TOP_tne,
- TOP_tnei,
- TOP_lwc1,
- TOP_ldc1,
- TOP_lwxc1,
- TOP_ldxc1,
- TOP_swc1,
- TOP_sdc1,
- TOP_swxc1,
- TOP_sdxc1,
TOP_abs_s,
TOP_abs_d,
TOP_add_s,
@@ -429,19 +253,6 @@
TOP_trunc_l_d,
TOP_bc1f,
TOP_bc1t,
- TOP_asm,
- TOP_intrncall,
- TOP_spadjust,
- TOP_begin_pregtn,
- TOP_end_pregtn,
- TOP_bwd_bar,
- TOP_fwd_bar,
-#if defined(TARG_SL) || defined(TARG_SL2)
- TOP_peripheral_rw_begin,
- TOP_peripheral_rw_end,
-#endif
- TOP_label,
-#ifdef TARG_SL2
TOP_c2_mvgr_r2g_h_u,
TOP_c2_mvgr_r2g_h,
TOP_c2_mvgr_r2g_w,
@@ -768,7 +579,7 @@
TOP_c2_sum4_saddr,
TOP_c2_med,
TOP_c2_fork_m,
- TOP_c2_fork_n ,
+ TOP_c2_fork_n,
TOP_c2_joint,
TOP_c2_ld_v2g_b_u,
TOP_c2_ld_v2g_b,
@@ -819,7 +630,194 @@
TOP_c2_shsub_l_i,
TOP_c2_shsub_rl_i,
TOP_c2_shsub_ra_i,
-#endif //TARG_SL2
+ TOP_UNDEFINED);
+
+ sl5 = ISA_Subset_Create(mips4, "SL5");
+
+ Instruction_Group(sl5,
+ TOP_loop,
+ TOP_mvtc,
+ TOP_mvfc,
+ TOP_mvtc_i,
+ TOP_ret,
+ TOP_abs16,
+ TOP_add16,
+ TOP_add16_i,
+ TOP_add16_sp,
+ TOP_and16,
+ TOP_and16_i,
+ TOP_jr16,
+ TOP_jr16_lnk,
+ TOP_ldw16,
+ TOP_ldub16_rs,
+ TOP_lduh16_rs,
+ TOP_mv16,
+ TOP_mv16_i,
+ TOP_mvfc16,
+ TOP_mvtc16,
+ TOP_nop16,
+ TOP_inv16,
+ TOP_or16,
+ TOP_or16_i,
+ TOP_pop16,
+ TOP_push16,
+ TOP_ret16,
+ TOP_shll16,
+ TOP_shll16_i,
+ TOP_shra16,
+ TOP_shra16_i,
+ TOP_shrl16,
+ TOP_shrl16_i,
+ TOP_stw16,
+ TOP_sub16,
+ TOP_sub16_i,
+ TOP_xor16,
+ TOP_xor16_i,
+ TOP_br16_eqz,
+ TOP_br16_nez,
+ TOP_lb,
+ TOP_lbu,
+ TOP_lh,
+ TOP_lhu,
+ TOP_lw,
+ TOP_lwl,
+ TOP_lwr,
+ TOP_sb,
+ TOP_sh,
+ TOP_sw,
+ TOP_swl,
+ TOP_swr,
+ TOP_ll,
+ TOP_sc,
+ TOP_lwu,
+ TOP_ld,
+ TOP_ldl,
+ TOP_ldr,
+ TOP_lld,
+ TOP_sd,
+ TOP_sdl,
+ TOP_sdr,
+ TOP_scd,
+ TOP_add,
+ TOP_addi,
+ TOP_addiu,
+ TOP_addu,
+ TOP_slt,
+ TOP_slti,
+ TOP_sltiu,
+ TOP_sltu,
+ TOP_smult,
+ TOP_sub,
+ TOP_subu,
+ TOP_dadd,
+ TOP_daddi,
+ TOP_daddiu,
+ TOP_daddu,
+ TOP_dsub,
+ TOP_dsubu,
+ TOP_and,
+ TOP_andi,
+ TOP_lui,
+ TOP_nor,
+ TOP_or,
+ TOP_ori,
+ TOP_xor,
+ TOP_xori,
+ TOP_mfhi,
+ TOP_mflo,
+ TOP_mthi,
+ TOP_mtlo,
+ TOP_mc_abs,
+ TOP_mc_zc_eq,
+ TOP_mc_zc_ne,
+ TOP_mc_zc_gt,
+ TOP_mc_zc_ge,
+ TOP_mc_zc_lt,
+ TOP_mc_zc_le,
+ TOP_mc_z_eq,
+ TOP_mc_z_ne,
+ TOP_mc_z_gt,
+ TOP_mc_z_ge,
+ TOP_mc_z_lt,
+ TOP_mc_z_le,
+ TOP_mc_zn_eq,
+ TOP_mc_zn_ne,
+ TOP_mc_zn_gt,
+ TOP_mc_zn_ge,
+ TOP_mc_zn_lt,
+ TOP_mc_zn_le,
+ TOP_mc_r_eq,
+ TOP_mc_r_ne,
+ TOP_mc_r_gt,
+ TOP_mc_r_ge,
+ TOP_mc_r_lt,
+ TOP_mc_r_le,
+ TOP_depb,
+ TOP_extrbs,
+ TOP_extrbu,
+ TOP_movf,
+ TOP_movn,
+ TOP_movt,
+ TOP_movz,
+ TOP_sll,
+ TOP_sllv,
+ TOP_sra,
+ TOP_srav,
+ TOP_srl,
+ TOP_srlv,
+ TOP_dsll,
+ TOP_dsll32,
+ TOP_dsllv,
+ TOP_dsra,
+ TOP_dsra32,
+ TOP_dsrav,
+ TOP_dsrl,
+ TOP_dsrl32,
+ TOP_dsrlv,
+ TOP_beq,
+ TOP_bgez,
+ TOP_bgezal,
+ TOP_bgtz,
+ TOP_blez,
+ TOP_bltz,
+ TOP_bltzal,
+ TOP_bne,
+ TOP_j,
+ TOP_jal,
+ TOP_jalr,
+ TOP_jr,
+ TOP_break,
+ TOP_syscall,
+ TOP_teq,
+ TOP_teqi,
+ TOP_tge,
+ TOP_tgei,
+ TOP_tgeiu,
+ TOP_tgeu,
+ TOP_tlt,
+ TOP_tlti,
+ TOP_tltiu,
+ TOP_tltu,
+ TOP_tne,
+ TOP_tnei,
+ TOP_lwc1,
+ TOP_ldc1,
+ TOP_lwxc1,
+ TOP_ldxc1,
+ TOP_swc1,
+ TOP_sdc1,
+ TOP_swxc1,
+ TOP_sdxc1,
+ TOP_asm,
+ TOP_intrncall,
+ TOP_spadjust,
+ TOP_begin_pregtn,
+ TOP_end_pregtn,
+ TOP_bwd_bar,
+ TOP_fwd_bar,
+ TOP_peripheral_rw_begin,
+ TOP_peripheral_rw_end,
+ TOP_label,
TOP_nop,
TOP_noop,
TOP_UNDEFINED);
------------------------------------------------------------------------------
Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)!
Finally, a world-class log management solution at an even better price-free!
Download using promo code Free_Logger_4_Dev2Dev. Offer expires
February 28th, so secure your free ArcSight Logger TODAY!
http://p.sf.net/sfu/arcsight-sfd2d
_______________________________________________
Open64-devel mailing list
Open64-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/open64-devel
