David,
Thanks for your patch and we're just waiting for it. Thank you for your
patient and continuously improvement.
Maybe isa-subset is not that useful for the x86 target, but it's
meaningful to the SL processors since they are quite changed from each other
and only share a common risc core. When I was merging the new patch to SL5,
our simplest case, I found I have to add plenty of fake SIs to statisfy the
SI full constraint and when new SL3 processor was added, the case is even
worse since all other processors have to upgrade.
We originally expect to see changes in x8664 proc dirs, you have done
more:) thanks for that. Due to Chinese spring festival, I'll merge, test and
report after the festival.
Gang
On Tue, Jan 25, 2011 at 5:22 AM, David Coakley <dcoak...@gmail.com> wrote:
> The attached patch si_subset.diff enables the target SI generator to
> work with ISA subsets. Previously I had not tested this case as no
> one was using it, but it looks like it is useful as a way to avoid
> having to explicitly list unsupported instructions in the set of dummy
> instructions. There are also a few minor changes to fix compilation
> warnings for si_gen.cxx. The generator still requires that you
> provide SI for all instructions in the processor's target ISA subset.
>
> The second patch, sl_example.diff, shows how to modify the definitions
> of the SL target to use a second ISA subset. I do not plan to check
> these changes in -- the patch is provided only as an example. Here, a
> common subset of instructions is factored out to form the SL5 subset.
> The instruction "smult" is added to the list of dummy instructions for
> the other targets -- it seems to be an odd case where it is supported
> by SL5 but not the other processors which otherwise support many more
> instructions, and I think it seems reasonable to require that it be
> listed as a dummy.
>
> Could a gatekeeper please review the first patch? Thanks,
>
> -David Coakley / AMD Open Source Compiler Engineering
>
>
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