please go ahead
Sun
On Fri, Feb 18, 2011 at 6:14 AM, David Coakley <dcoak...@gmail.com> wrote:
> Hi Gang,
>
> Thank you for testing and correcting the patch. I have revised my
> original patch to include your change to isa_subset_gen.cxx below.
> This patch does not include any target-specific code and should not
> affect the existing targets -- it just clears the way for future use
> of ISA subsets.
>
> Could a gatekeeper review the attached patch? This will complete the
> targ_info changes that I have already checked in for the current
> release. Thanks,
>
> -David Coakley / AMD Open Source Compiler Engineering
>
> On Tue, Feb 15, 2011 at 1:20 AM, Gang Yu <yugang...@gmail.com> wrote:
>> David,
>>
>> I have made isa subset patch work under SL target. However, the following
>> should be patched together.
>>
>> Index: osprey/common/targ_info/generate/isa_subset_gen.cxx
>> ===================================================================
>> --- osprey/common/targ_info/generate/isa_subset_gen.cxx (revision 3476)
>> +++ osprey/common/targ_info/generate/isa_subset_gen.cxx (working copy)
>> @@ -264,7 +264,17 @@
>> fprintf(cfile," { /* %s */\n", subset->name);
>> for ( unsigned int i = 0; i < bit_vector_sizeof; ++i ) {
>> - int members = subset->members[i];
>> + int members=0;
>> + for (int j = 0; j < 8; ++j ) {
>> + TOP top = (TOP) ((i * 8) + j);
>> + ISA_SUBSET ss;
>> + for (ss = subset; ss != NULL ; ss = ss->superset) {
>> + if (opcode_subset[top] == ss) {
>> + members |= 1 << j;
>> + break;
>> + }
>> + }
>> + }
>> fprintf(cfile," 0%03o, /* ",members);
>> for (int j = 0; j < 8; ++j) {
>> if (members & (1 << j)) {
>> Without the patch, insns in superset are lost in the targ_isa_subset.c and
>> treated as dummy insns which leads to the wrong scheduling. I have run
>> several test cases and build up the SL app code , it seems no changes in the
>> code. For targets do not use isa subset, it will make no change to code
>> production.
>>
>> Attaches are patches for SL's isa subset.
>>
>> Gang
>>
>>
>> On Tue, Jan 25, 2011 at 5:22 AM, David Coakley <dcoak...@gmail.com> wrote:
>>>
>>> The attached patch si_subset.diff enables the target SI generator to
>>> work with ISA subsets. Previously I had not tested this case as no
>>> one was using it, but it looks like it is useful as a way to avoid
>>> having to explicitly list unsupported instructions in the set of dummy
>>> instructions. There are also a few minor changes to fix compilation
>>> warnings for si_gen.cxx. The generator still requires that you
>>> provide SI for all instructions in the processor's target ISA subset.
>>>
>>> The second patch, sl_example.diff, shows how to modify the definitions
>>> of the SL target to use a second ISA subset. I do not plan to check
>>> these changes in -- the patch is provided only as an example. Here, a
>>> common subset of instructions is factored out to form the SL5 subset.
>>> The instruction "smult" is added to the list of dummy instructions for
>>> the other targets -- it seems to be an odd case where it is supported
>>> by SL5 but not the other processors which otherwise support many more
>>> instructions, and I think it seems reasonable to require that it be
>>> listed as a dummy.
>>>
>>> Could a gatekeeper please review the first patch? Thanks,
>>>
>>> -David Coakley / AMD Open Source Compiler Engineering
>>>
>>>
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>>
>>
>
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http://p.sf.net/sfu/intel-dev2devfeb
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