On Tue, Sep 15, 2026 at 12:03 PM Trevor Gamblin <[email protected]> wrote:
> There are currently many RISC-V ISA extensions missing from the > arch-riscv.inc file, even some which are required by core 'riscv64gc' > extensions. For example: > > |tgamblin@megalith > ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ > riscv64-linux-gnu-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -Q > --help=target | grep rv64 > | -march= > rv64imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd > > versus: > > |TUNE_FEATURES = "rv 64 i m a f d c zicsr zifencei" > > which is missing zmmul, zaamo, zalrsc, zca, and zcd. There are even more > absent when comparing against the official RVA20 spec - passing > '-march=rva20u64' to gcc and checking the ISA extension string shows: > > |tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d > -Q --help=target | grep rv64 > | -march= > rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd > > Add the following extensions to arch-riscv.inc, along with their > conditional inclusions required: > > - za128rs > - zaamo (required by 'a') > - zalrsc (required by 'a') > - zca (required by 'c') > - zcd > - ziccamoa > - ziccif > - zicclsm > - ziccrse > - zicntr > - zmmul (required by 'm') > > We also need to change the extension ordering in the file, so that they > appear in the same order as the compiler expects. > > Signed-off-by: Trevor Gamblin <[email protected]> > --- > .../conf/machine/include/riscv/arch-riscv.inc | 46 ++++++++++++++++++- > 1 file changed, 45 insertions(+), 1 deletion(-) > > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc > b/meta/conf/machine/include/riscv/arch-riscv.inc > index 6f9b74974d..7db400694c 100644 > --- a/meta/conf/machine/include/riscv/arch-riscv.inc > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc > @@ -86,14 +86,58 @@ TUNEVALID[zicbom] = "Cache-block management extension" > TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", > "_zicbom", "", d)}" > TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", > "zicbom", "_zicbom", "", d)}" > > +TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", > "_ziccamoa", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", > "_ziccamoa", "", d)}" > + > +TUNEVALID[ziccif] = "Patching instructions at run time extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", > "_ziccif", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", > "_ziccif", "", d)}" > + > +TUNEVALID[zicclsm] = "Software that assumes misaligned access works > extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", > "_zicclsm", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", > "_zicclsm", "", d)}" > + > +TUNEVALID[ziccrse] = "Guarantees LR/SC forward progress extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", > "_ziccrse", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", > "_ziccrse", "", d)}" > + > +TUNEVALID[zicntr] = "Cycle and instruction counting for profiling > extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", > "_zicntr", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", > "_zicntr", "", d)}" > + > TUNEVALID[zicsr] = "Control and status register access extension" > TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f > d", "_zicsr", "", d)}" > TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f > d", "_zicsr", "", d)}" > > -TUNEVALID[zifencei] = "Instruction-fetch fence extension" > +TUNEVALID[zifencei] = "Instruction-fetch fence extension." > TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", > "_zifencei", "", d)}" > TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", > "_zifencei", "", d)}" > > +TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", > "_zmmul", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", > "_zmmul", "", d)}" > It uses contains (AND) where it means "implied by" (OR). bb.utils.contains("TUNE_FEATURES", "m zmmul", ...) fires only when both m and zmmul are present. Net effect: the commit message's premise — riscv64gc is missing zmmul/zaamo/zalrsc/zca/zcd relative to gcc — is not fixed, riscv64gc still yields -march=rv64imafdc_zicsr_zifencei while gcc expands rv64gc to ..._zmmul_zaamo_zalrsc_zca_zcd. Either switch to contains_any (and own the default-tune -march/pkgarch churn) or reword the commit message because as-is the lines are dead for every non-profile tune. zcd has the same issue (gcc implies it from c+d). > + > +TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", > "_za128rs", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", > "_za128rs", "", d)}" > + > +TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", > "_zaamo", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", > "_zaamo", "", d)}" > + > +TUNEVALID[zalrsc] = "Extended LR/SC semantics extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", > "_zalrsc", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", > "_zalrsc", "", d)}" > + > +TUNEVALID[zca] = "Compressed base integer ops extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", > "_zca", "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", > "_zca", "", d)}" > + > +TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension." > +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", > "", d)}" > +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", > "_zcd", "", d)}" > + > TUNEVALID[zba] = "Address bit manipulation extension" > TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", > "_zba", "", d)}" > TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", > "_zba", "", d)}" > -- > 2.55.0 > >
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