On Fri, 2006-08-25 at 09:53 -0700, Roland Dreier wrote: > Sean> Couldn't the same point then be made that a CQ entry may > Sean> come before the data has been posted? > > That's true -- I guess I need to look at what ordering guarantees the > PCI spec makes to give a real answer. >
I believe bus bridges between devices and memory _must_ ensure write ordering. Otherwise nothing works, right? _______________________________________________ openib-general mailing list openib-general@openib.org http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
