In message <[EMAIL PROTECTED]>,Roland Dreier writes: >That says you should do a read to flush writes, doesn't it?? What am >I missing.
i guess my point is that you dont need to read from the device, you could read from the bridge or a config register. >The read that is failing is not going to DDR memory -- it going to a >"safe" register. i believe by safe register they meant the pci config register space and not the memory mapped registers on the card. looking at the trace from the analyzer, there are a couple writes to config register (config reg 1, PCI_COMMAND_IO) and then a read from the memory mapped region. i would guess the read to the mmio region is flushing the writes to the config register but the read happens "too soon" after those writes. on a more mundance computer, the write/write/read probably wouldnt be batched together. _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
