-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Somebody in the thread at some point said:
|> 1) enable_irq_wake(S3C_EINT(4)); fails, it should be OK to enable EINT4 |> as a wake source | | Without any of the power management there is no set_wake methods set on the | interrupts. Ah OK then. |> 2) s3c6400-uart: probe of s3c6400-uart.3 failed with error -22 |> |> But there are 4 UARTs on S3C6410 | | I'll update the Samsung serial driver to support 4 UARTs instead of 3. Great. On GTA03 debug console happens to be on the fourth one. |> 3) We did not fit the 27MHz clock on S3C6410, so we need to disable it |> system-wide as a clk source... eg for MMC base clock... what's the best |> way to do that? | | This information will be available in the platform data registered with | the system. OK I take that it means it will be exposed to the machine-specific stuff at some point later... in the meanwhile I will patch arch/arm/plat-s3c64xx/s3c6400-clock.c or stuff around there since it seems to select 27MHz clock as the default source for the HS_MMC0[1]. [ 0.000000] mmc_bus: source is clk_27m (3), rate is 27000000 |> 4) HS_MMC is a valid platform device and is initialized, but it doesn't |> see the SDHC card. Assuming this is missing somewhat, what's the status |> on it? | | Furhter testing is being done on the SDHCI, will release a set of what | I consider stable later today. Great it will be very handy to be able to mount a rootfs from there and do SDIO. Thanks, - -Andy [1] This nearly caused a heart attack when I noticed it yesterday since it looked like the iROM was using the (NC on GTA03) 27MHz source, but I verified in bootloader it's EPll. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org iEYEARECAAYFAkkOxfIACgkQOjLpvpq7dMpVUACcC1PsOtbtIW5HttI4Ki0mEmU8 +vsAn3pGSrhF9za5BH0mhS5G69vGShs2 =NDVy -----END PGP SIGNATURE-----
