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Somebody in the thread at some point said:
| Somebody in the thread at some point said:
|
| | CLK_SRC is 0x00002007 early in the bootloader, b19b18 = 00 = MMC0 =
| | MOUTepll; 11 there would be 27MHz source. I didn't spot where the
| | bootloader MMC stuff changes the clock source to 27MHz, so something is
| | fishy somewhere.
|
| |> -#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1)
| |> -#define S3C6400_CLKSRC_MMC0_SHIFT (1)
| |> +#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
| |> +#define S3C6400_CLKSRC_MMC0_SHIFT (18)
|
| |> merged into s3c64xx and pushed out.
|
| Thanks for the fix.
This is solved
[ 0.000000] mmc_bus: source is mout_epll (0), rate is 24000000
but the fourth UART is still borked
[42949376.300000] s3c6400-uart: probe of s3c6400-uart.3 failed with
error -22
static struct s3c2410_uartcfg om_gta03_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
};
- -Andy
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