On Thu, Feb 09, 2012 at 02:40:21PM +0100, [email protected] wrote: > Hi, > Thank you for your reply. > MIPS CPU is Broadcom BCM 7401. > I tested it further and found out that if HALT state, > SDRAM provides only 0s( zeros). > I think it is logical, because the internal processor system bus clock > was stopped and SDRAM is not refreshed. > Or am I wrong? > > I think DEBUG state would be better, but I can not bring the CPU > (BCM 7401) into Debug state. > Only into HALT state. > > I tried to set control register values(bits) > PrACc,ProbEn,ProbTrap and JtagBrk > but when I read control register values(after writing PrACc,ProbEn,ProbTrap > and JtagBrk > into contol register) > BRKST ( bit 3 of the control register) is still 0 , not set.
Maybe someone can help. My experience with Broadcom is they do not release information openly. Do you have URLs for the BCM7401 data sheet / HRM (hardware reference manual) / etc? Perhaps an earlier BCM CPU data sheet is available that will help. John ------------------------------------------------------------------------------ Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
