On Thu, Feb 9, 2012 at 2:40 PM, <[email protected]> wrote: > Hi, > Thank you for your reply. > MIPS CPU is Broadcom BCM 7401. > I tested it further and found out that if HALT state, > SDRAM provides only 0s( zeros). > I think it is logical, because the internal processor system bus clock > was stopped and SDRAM is not refreshed. > Or am I wrong?
Did you set-up your SDRAM controller ? > > I think DEBUG state would be better, but I can not bring the CPU > (BCM 7401) into Debug state. > Only into HALT state. How did you brought it into HALT state skipping the DEBUG ? > > I tried to set control register values(bits) > PrACc,ProbEn,ProbTrap and JtagBrk How did you set them up, not being in the DEBUG interrupt ? > but when I read control register values(after writing PrACc,ProbEn,ProbTrap > and JtagBrk > into contol register) > BRKST ( bit 3 of the control register) is still 0 , not set. How do you read ? I am interested what functions are you using ? BR, Drasko ------------------------------------------------------------------------------ Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
