Drasko ,
Thank you for your reply.
> and where can I find out mips_ejtag_enter_debug() function?
I meant in source code, where I can find out that
mips_ejtag_enter_debug() function.
>
> Find a EJTAG manual. It is a first hit on a Google. In Table 6-9 EJTAG
> Control Register Field Descriptions you will see EjtagBrk (bit 12 of EJTAG
> control register) explained.
Yes, I used that
EjtagBrk. But CPU did not go into Debug mode.
Is that only this
EjtagBrk that should cause CPU to start Debug mode?
Or issuing
EJTAGBOOT instruction itself should cause Debug mode?
>
> > I think DEBUG state would be better, but I can not bring the CPU
> > (BCM 7401) into Debug state.
> > Only into HALT state.
> >
> > I tried to set control register values(bits)
> > PrACc,ProbEn,ProbTrap and JtagBrk
>
> How ?
>
I wrote
CONTROL instruction into Instruction register of EJTAG Test Access Port (TAP) and then
PrACc,ProbEn,ProbTrap and JtagBrk bits into Data register .
Then I read data register to find out if CPU is in Debug mode( bit 3 is 1 if in Debug).But was
0.
But Halt bit was set( and as a result the device with that CPU stopped working - seemed like
being hanged)
> How did you brought it into HALT state skipping the DEBUG ?
Do you mean that Debug mode must be first? In other words HALT can not be issued from
non Debug state?
> > but when I read control register values(after writing
> PrACc,ProbEn,ProbTrap and JtagBrk
> > into contol register)
>
> How do you read ?
>From data register of
EJTAG Test Access Port (TAP).
Thanks for the replies
------------------------------------------------------------------------------ Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/
_______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
