Ken Smith wrote: > Thanks for all the responses and links! Peter, the separate SRAM's I'm > talking about are the separate memories for instruction and code that > pertain, I think, to the Harvard architecture of the chip. I read > somewhere that the memories can only be used for certain purposes.
That's "only" locally in the CPU. From the user manual: * Up to 64 kB on-chip SRAM includes: – Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. – Up to two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose instruction and data storage. On the (internal) bus it's all one address space. > I'm also intrigued by this eval board. > > http://olimex.com/dev/lpc-1766stk.html > > It is more well equipped with some of the things I'll eventually want. Note none of the examples are for GCC, so you may need to rework them (hours and hours) just to build them without a proprietary toolchain. The reference code from NXP was ported to GCC by 32bitmicro.com. The code is a big Makefile mess, but does work. http://code.google.com/p/32bitmicro/wiki/LPC17xxSampleSoftware http://code.google.com/p/32bitmicro/source/browse/#svn%2Ftrunk%2Fsrc%2Fnxp%2Flpc17xx%2FLPC17xxSampleSoftware //Peter ------------------------------------------------------------------------------ Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
