On Wed, Oct 30, 2013 at 12:15 PM, Brian Jones <[email protected]>wrote:
> Hi All,
>
What Jens said plus some additional comments below.
>
>
>> I'm hoping you can give me a hand here. I'm trying to debug a custom
>> board (aka not a standard development board, etc) which has the EM357 chip.
>> I'm using a Bus Blaster v3c as the OpenOCD interface, using the config file
>> shown below.
>>
>> I'm new to OpenOCD, and -- unfortunately -- even after reading the docs I
>> could find and some prior mailing list posts which looked related to EM357
>> chips, I couldn't get it to work:
>>
>> $ openocd -f openocd.cfg
>> Open On-Chip Debugger 0.5.0 (2011-12-03-10:15)
>>
>
Yes, this is very old. Please use at least 0.7.0 or even better compile
your own from git HEAD. Not that I think it will help with your specific
problem.
Licensed under GNU GPL v2
>> For bug reports, read
>> http://openocd.berlios.de/doc/doxygen/bugs.html
>> Info : only one transport option; autoselect 'jtag'
>> 500 kHz
>> adapter_nsrst_delay: 100
>> jtag_ntrst_delay: 100
>> cortex_m3 reset_config sysresetreq
>> 500 kHz
>> Info : max TCK change to: 30000 kHz
>> Info : clock speed 500 kHz
>> Error: JTAG scan chain interrogation failed: all ones
>>
>>
> I'm connected to JRST, JTMS, JTDI, JTDO, JTCK on the EM357, in addition to
>> having the Bus Blaster tied to GND and VREF (I think I have the right test
>> point for this one).
>>
>
Make sure you have the right signal connected to JRST. The naming doesn't
suggest whether it resets the TAP (commonly called TRST) or the system
(commonly called SRST). If you have a voltmeter, you should check that VREF
is at around 3 V. And continuity test the other wires.
>> Here are my config files:
>>
>> $ cat busblaster.cfg
>> # Bus Blaster
>> #
>> # http://dangerousprototypes.com/docs/Bus_Blaster
>> #
>>
>> interface ft2232
>> ft2232_device_desc "Dual RS232-HS"
>> ft2232_layout jtagkey
>> ft2232_vid_pid 0x0403 0x6010
>>
>> $ cat openocd.cfg
>> source [find busblaster.cfg]
>>
>
If you upgrade, change this to "source [find
interface/ftdi/dp_busblaster.cfg]"
set CHIPNAME em357
>> source [find target/stm32f1x.cfg]
>> jtag_khz 500
>>
>
Try even lower, say 10 kHz, to rule out speed problems (I have no idea what
the CPU freq of the em357 is after boot).
Another question is what is running on the CPU. If it's loaded with some
arbitrary firmware, it might put the MCU into sleep mode which would make
it hard or impossible to connect to it while it's running. The firmware
could even reconfigure the JTAG pins to regular GPIOs. In those cases, the
only option is to make sure that SRST (not TRST) is controlled by OpenOCD
so that it can be pulled down during target examination and halted before
the first instruction. More recent OpenOCD have better support for this
procedure.
/Andreas
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