hi all:
2014-09-04 16:40 GMT+08:00 vichy <[email protected]>:
> hi all:
> I have some question about cortex_a_read_apb_ab_memory in cortex_a.c
> From spec,
> "A write to the DBGITR does not trigger an instruction for execution.
> Instead, the debug logic latches the
> instruction written to DBGITR, and retains this value until either a
> new value is written to DBGITR, or
> software changes the access mode. "
>
> But in the beginning of cortex_a_read_apb_ab_memory, we use
> u8buf_ptr[2] to put ITR instructions and DSCR with DCC_FAST_MODE
> that mean the 1st ITR instruction will be executed, since DCC is not
> FAST_MODE at that time.
> Shall we change the flow like below?
> thanks for your help in advance,
>
I change modification like below.
The modification in the previous mail is wrong for assigning the buffer order.
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
old mode 100644
new mode 100755
index 7d58ab3..bc14273
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1953,7 +1953,6 @@ static int cortex_a_read_apb_ab_memory(struct
target *target,
struct reg *reg;
uint32_t dscr;
uint8_t *tmp_buff = NULL;
- uint8_t buf[8];
uint8_t *u8buf_ptr;
LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32 " size %"
PRIu32 " count%" PRIu32,
@@ -2004,13 +2003,9 @@ static int cortex_a_read_apb_ab_memory(struct
target *target,
* and the DTR mode setting to fast mode
* in one combined write (since they are adjacent registers)
*/
- u8buf_ptr = buf;
- target_buffer_set_u32(target, u8buf_ptr, ARMV4_5_LDC(0, 1, 0,
1, 14, 5, 0, 4));
dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE;
- target_buffer_set_u32(target, u8buf_ptr + 4, dscr);
- /* group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */
- retval += mem_ap_sel_write_buf(swjdp, armv7a->debug_ap, u8buf_ptr, 4, 2,
- armv7a->debug_base + CPUDBG_ITR);
+ retval +=
mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base
+ CPUDBG_DSCR,dscr);
+ retval +=
mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base
+ CPUDBG_ITR,ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
goto error_unset_dtr_r;
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