Il 15/06/2016 11:45, Andreas Fritiofson ha scritto:
In the latter case, you use some weird custom scripts containing the
old soft_reset_halt command. None of the stock cortex_m configs
contain that command. Make sure you're not sourcing some old scripts.
The first case seems to use the stock configs only, good. But it still
fails. Are you saying GDB can load with the same setup but not from
command line?
Didn't you say you had some corrupted option bytes on the target that
failed programming? Have you restored them? Or do they keep getting
corrupt? Especially the HW IWDG option can/will interfere with the
flashing algorithm. I suspect the "unlock" argument if the option
bytes get corrupted by OpenOCD. That step is not performed as part of
GDB load. Perhaps write (un-)protection is not supported for the F7, Uwe?
By the way, for flashing from the command line, use the "program"
script. E.g.
openocd -f board/stm32f7discovery.cfg -c
"program Debug-MB1191B-0/LCDTest.elf verify reset exit"
/Andreas
The problem for not correct programmer was in effect caused by option bytes.
We tried to flash STM32F7 discovery board with ST LINK using OpenOCD
with the script 'program' and it works with Linux and in Windows with
the STLink Utilities.
The problem remains with OUR Board (EK390) BUT only in Linux using
OpenOCD and STLink hardware. Using Windows and STLink Utlities our board
is correctly programmed, so we can for sure assert that the hardware is
good enough.
With 'PROGRAM':
openocd -f board/stm32f7discovery.cfg -c "program
Debug-EK390-0/LCDTest.elf verify reset exit"
Open On-Chip Debugger 0.10.0-dev-00321-gd4b7cbf (2016-05-31-10:18)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The
results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v24 API v2 SWIM v11 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.258498
Warn : Silicon bug: single stepping will enter pending exception handler!
Info : stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints
Error: timed out while waiting for target halted
TARGET: stm32f7x.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 478
in procedure 'ocd_bouncer'
** Unable to reset target **
shutdown command invoked
With 'WRITE FLASH' but without 'UNLOCK':
openocd -f interface/stlink-v2-1.cfg -f
/home/lorenzo/Progetti/EcceGui/demo/myboard_EK390.cfg -c "init;
targets; reset init; poll; flash write_image erase
Debug-EK390-0/LCDTest.elf; flash erase_check 0; reset run; shutdown"
Open On-Chip Debugger 0.10.0-dev-00321-gd4b7cbf (2016-05-31-10:18)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "hla_swd". To
override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The
results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
adapter speed: 600 kHz
Info : Unable to match requested speed 600 kHz, using 480 kHz
Info : Unable to match requested speed 600 kHz, using 480 kHz
Info : clock speed 480 kHz
Info : STLINK v2 JTAG v24 API v2 SWIM v11 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.258498
Warn : Silicon bug: single stepping will enter pending exception handler!
Info : stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* stm32f7x.cpu hla_target little stm32f7x.cpu running
Error: timed out while waiting for target halted
TARGET: stm32f7x.cpu - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'
Any hint?
--
*Lorenzo Corti* | Ricerca e Sviluppo
*Eurek s.r.l. *Via Celletta 8/b | 40026 Imola (BO) - Italy | +39 *0542
609120*
[email protected] <mailto:[email protected]> | www.eurek.it
<http://www.eurek.it/>
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