By the way, arm errata reports that there is no HW fix, yet; all the Cortex-M7 today in production should have this bug. This mail's subject mentions STM, but the issue should be more general.
Antonio On Sat, Jun 8, 2024, 15:48 Antonio Borneo <borneo.anto...@gmail.com> wrote: > We also detect the CPU as Cortex-M7 with cortex_m->core_info. > There could be an additional check to restrict the workaround to Cortex-M7 > only. > > Antonio > > On Fri, Jun 7, 2024, 13:02 Liviu Ionescu <i...@livius.net> wrote: > >> >> >> > On 7 Jun 2024, at 12:23, Tomas Vanek <tom_...@users.sourceforge.net> >> wrote: >> > >> > The workaround in OpenOCD cortex_m.c cortex_m_debug_entry() should >> check the DFSR register >> > and if the only BKPT bit is set, than check if PC points to a BKPT >> instruction or any FPB >> > FP_COMPn has triggered the break and if not, then OpenOCD could resume. >> >> If I remember right, this was my proposal too. Possibly with a warning >> message. >> >> Liviu >> >> >> >> >>
