> On 8 Jun 2024, at 16:55, Antonio Borneo <borneo.anto...@gmail.com> wrote:
>
> By the way, arm errata reports that there is no HW fix, yet; all the
> Cortex-M7 today in production should have this bug.
> This mail's subject mentions STM, but the issue should be more general.
Right, it was noticed on one of my old STM boards, but by that time we could
not test it on other CM7 implementations.
But Joseph Yiu from Arm confirmed the issue right away, by running the failing
example on an FPGA with their latest implementation.
The bug affects not only semihosting test applications like my tests, it
affects also regular applications, the faster the interrupt rate (like for
applications using fast USB transfers) the higher the probability to get a
rogue breakpoint in the interrupt handler. This case was confirmed by a
colleague, it was a common occurrence in his debug sessions. He also mentioned
that there were some discussions in the STM forums, but by that time the cause
was not known.
I'm curious how long it'll take Arm to release a new CM7 core implementation
and how long it'll take to vendors to release new devices based on it...
Liviu
