On Sat, Jun 28, 2008 at 11:29 AM, Pavel Chromy <[EMAIL PROTECTED]> wrote: > Hello ?yvind, > > ?yvind Harboe napsal(a): >> >> Basically a TMS reset happens while srst is asserted. This is >> probably to drive the state machine into TAP_TLR as srst >> pulls trst to sync up things. >> >> A cleaner way would be to simply set the tracked state >> to TAP_TLR. > > This is not sufficient in all cases. If there is a part which does not > feature TRST hooked > up in the JTAG chain (e.g. FPGA) transition to TLR by means of TMS is > a necessity to keep all parts in sync. > > I am going to test this soon, we have a board with this configuration in the > manufacturing > (AT91SAM9260 with SRST pulling TRST + an FPGA without TRST)
I'd say this is just one more argument for scriptable reset. There is no way we'll be able to come up with an algorithm & config parameters something that can cover all the weird reset schemes out there.... I'm trying to summarize a consensus + plan here.... http://svn.berlios.de/svnroot/repos/openocd/trunk/src/scripting.txt -- Øyvind Harboe http://www.zylin.com/zy1000.html ARM7 ARM9 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
