Øyvind Harboe wrote:
> I'm going to be out of the office for the next week, so I'm turning into
> a pumpkin RSN.
>
> omap3_dbginit should be made part of the reset sequence.
>
> OpenOCD supports hot-plugging of targets. Feel free to scream, but this
> is something that developers do since it saves time. If it bricks a
> beagleboard
> a year, it is still a bargain :-)
>
> There is a *slight* bit of autoconfiguration going on with OpenOCD. The
> target is examined (during startup and/or reset sequence) so that e.g.
> version of debug hardware and hardware capabilities can be read out
> and OpenOCD structures can be set up.
>
> I believe the best approach with OMAP would be to set up the entire
> JTAG system during reset and not rely on rexamine upon startup.
>
> Try the attached patch and call in the morning...
Are you sure that you attached the right patch? The attached one seems
to be a src/target/cortex_m3.c whitespace fix one, only? See below.
Best regards
Dirk
Index: src/target/cortex_m3.c
===================================================================
--- src/target/cortex_m3.c (revision 1805)
+++ src/target/cortex_m3.c (working copy)
@@ -63,7 +63,7 @@
.arch_state = armv7m_arch_state,
.target_request_data = cortex_m3_target_request_data,
-
+
.halt = cortex_m3_halt,
.resume = cortex_m3_resume,
.step = cortex_m3_step,
@@ -71,7 +71,7 @@
.assert_reset = cortex_m3_assert_reset,
.deassert_reset = cortex_m3_deassert_reset,
.soft_reset_halt = cortex_m3_soft_reset_halt,
-
+
.get_gdb_reg_list = armv7m_get_gdb_reg_list,
.read_memory = cortex_m3_read_memory,
@@ -79,9 +79,9 @@
.bulk_write_memory = cortex_m3_bulk_write_memory,
.checksum_memory = armv7m_checksum_memory,
.blank_check_memory = armv7m_blank_check_memory,
-
+
.run_algorithm = armv7m_run_algorithm,
-
+
.add_breakpoint = cortex_m3_add_breakpoint,
.remove_breakpoint = cortex_m3_remove_breakpoint,
.add_watchpoint = cortex_m3_add_watchpoint,
@@ -151,12 +151,12 @@
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
-
+
return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
@@ -166,10 +166,10 @@
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
-
+
/* Read Debug Fault Status Register */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume
?? Try with and without this !! */
@@ -186,20 +186,20 @@
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dhcsr_save;
-
+
/* backup dhcsr reg */
dhcsr_save = cortex_m3->dcb_dhcsr;
-
+
....
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