I'm going to be out of the office for the next week, so I'm turning into
a pumpkin RSN.
omap3_dbginit should be made part of the reset sequence.
OpenOCD supports hot-plugging of targets. Feel free to scream, but this
is something that developers do since it saves time. If it bricks a beagleboard
a year, it is still a bargain :-)
There is a *slight* bit of autoconfiguration going on with OpenOCD. The
target is examined (during startup and/or reset sequence) so that e.g.
version of debug hardware and hardware capabilities can be read out
and OpenOCD structures can be set up.
I believe the best approach with OMAP would be to set up the entire
JTAG system during reset and not rely on rexamine upon startup.
Try the attached patch and call in the morning...
--
Øyvind Harboe
Embedded software and hardware consulting services
http://consulting.zylin.com
### Eclipse Workspace Patch 1.0
#P openocd
Index: src/target/cortex_m3.c
===================================================================
--- src/target/cortex_m3.c (revision 1805)
+++ src/target/cortex_m3.c (working copy)
@@ -63,7 +63,7 @@
.arch_state = armv7m_arch_state,
.target_request_data = cortex_m3_target_request_data,
-
+
.halt = cortex_m3_halt,
.resume = cortex_m3_resume,
.step = cortex_m3_step,
@@ -71,7 +71,7 @@
.assert_reset = cortex_m3_assert_reset,
.deassert_reset = cortex_m3_deassert_reset,
.soft_reset_halt = cortex_m3_soft_reset_halt,
-
+
.get_gdb_reg_list = armv7m_get_gdb_reg_list,
.read_memory = cortex_m3_read_memory,
@@ -79,9 +79,9 @@
.bulk_write_memory = cortex_m3_bulk_write_memory,
.checksum_memory = armv7m_checksum_memory,
.blank_check_memory = armv7m_blank_check_memory,
-
+
.run_algorithm = armv7m_run_algorithm,
-
+
.add_breakpoint = cortex_m3_add_breakpoint,
.remove_breakpoint = cortex_m3_remove_breakpoint,
.add_watchpoint = cortex_m3_add_watchpoint,
@@ -151,12 +151,12 @@
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
-
+
return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
@@ -166,10 +166,10 @@
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
-
+
/* Read Debug Fault Status Register */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume ??
Try with and without this !! */
@@ -186,20 +186,20 @@
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dhcsr_save;
-
+
/* backup dhcsr reg */
dhcsr_save = cortex_m3->dcb_dhcsr;
-
+
/* mask interrupts if not done already */
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS |
C_HALT | C_DEBUGEN);
mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP
| C_DEBUGEN);
LOG_DEBUG(" ");
-
+
/* restore dhcsr reg */
- cortex_m3->dcb_dhcsr = dhcsr_save;
+ cortex_m3->dcb_dhcsr = dhcsr_save;
cortex_m3_clear_halt(target);
-
+
return ERROR_OK;
}
@@ -210,14 +210,14 @@
swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 savedram;
int retvalue;
-
+
mem_ap_read_u32(swjdp, 0x20000000, &savedram);
mem_ap_write_u32(swjdp, 0x20000000, opcode);
cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15);
cortex_m3_single_step_core(target);
armv7m->core_cache->reg_list[15].dirty =
armv7m->core_cache->reg_list[15].valid;
retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram);
-
+
return retvalue;
}
@@ -239,28 +239,28 @@
{
int i;
u32 dcb_demcr;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
- cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
+ cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
-
+
/* this regsiter is used for emulated dcc channel */
mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
-
+
/* Enable debug requests */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
-
+
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
-
+
/* Enable trace and dwt */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
/* Monitor bus faults */
@@ -275,7 +275,7 @@
{
target_write_u32(target, fp_list[i].fpcr_address,
fp_list[i].fpcr_value);
}
-
+
/* Restore DWT registers */
for (i = 0; i < cortex_m3->dwt_num_comp; i++)
{
@@ -284,12 +284,12 @@
target_write_u32(target, dwt_list[i].dwt_comparator_address |
0x8, dwt_list[i].function);
}
swjdp_transaction_endcheck(swjdp);
-
+
armv7m_invalidate_core_regs(target);
-
+
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
-
+
return ERROR_OK;
}
@@ -301,7 +301,7 @@
/* THIS IS NOT GOOD, TODO - better logic for detection of debug state
reason */
/* only check the debug reason if we don't know it already */
-
+
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
@@ -342,11 +342,11 @@
break;
case 4: /* Memory Management */
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
break;
case 5: /* Bus Fault */
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
break;
case 6: /* Usage Fault */
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
@@ -434,15 +434,15 @@
armv7m->core_mode =
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
armv7m->exception_number = 0;
}
-
+
if (armv7m->exception_number)
{
cortex_m3_examine_exception_reason(target);
}
- LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x,
target->state: %s",
+ LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x,
target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
- *(u32*)(armv7m->core_cache->reg_list[15].value),
+ *(u32*)(armv7m->core_cache->reg_list[15].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state
)->name);
if (armv7m->post_debug_entry)
@@ -455,7 +455,7 @@
{
int retval;
enum target_state prev_target_state = target->state;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
@@ -468,19 +468,19 @@
target->state = TARGET_UNKNOWN;
return retval;
}
-
+
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
/* check if still in reset */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
-
+
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
target->state = TARGET_RESET;
return ERROR_OK;
}
}
-
+
if (target->state == TARGET_RESET)
{
/* Cannot switch context while running so endreset is called
with target->state == TARGET_RESET */
@@ -489,7 +489,7 @@
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
}
-
+
if (cortex_m3->dcb_dhcsr & S_HALT)
{
target->state = TARGET_HALTED;
@@ -498,7 +498,7 @@
{
if ((retval = cortex_m3_debug_entry(target)) !=
ERROR_OK)
return retval;
-
+
target_call_event_callbacks(target,
TARGET_EVENT_HALTED);
}
if (prev_target_state == TARGET_DEBUG_RUNNING)
@@ -510,7 +510,7 @@
target_call_event_callbacks(target,
TARGET_EVENT_DEBUG_HALTED);
}
}
-
+
/*
if (cortex_m3->dcb_dhcsr & S_SLEEP)
target->state = TARGET_SLEEP;
@@ -521,27 +521,27 @@
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s",
cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple(
nvp_target_state, target->state )->name );
#endif
-
+
return ERROR_OK;
}
int cortex_m3_halt(target_t *target)
{
- LOG_DEBUG("target->state: %s",
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state
)->name);
-
+
if (target->state == TARGET_HALTED)
{
LOG_DEBUG("target was already halted");
return ERROR_OK;
}
-
+
if (target->state == TARGET_UNKNOWN)
{
LOG_WARNING("target was in unknown state when halt was
requested");
}
-
- if (target->state == TARGET_RESET)
+
+ if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
@@ -554,8 +554,8 @@
* debug entry was already prepared in
cortex_m3_prepare_reset_halt()
*/
target->debug_reason = DBG_REASON_DBGRQ;
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
}
@@ -563,7 +563,7 @@
cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
target->debug_reason = DBG_REASON_DBGRQ;
-
+
return ERROR_OK;
}
@@ -578,8 +578,8 @@
/* Enter debug state on reset, cf. end_reset_event() */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR |
VC_CORERESET);
-
- /* Request a reset */
+
+ /* Request a reset */
mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY |
AIRCR_VECTRESET);
target->state = TARGET_RESET;
@@ -604,7 +604,7 @@
timeout++;
alive_sleep(1);
}
-
+
return ERROR_OK;
}
@@ -614,49 +614,49 @@
armv7m_common_t *armv7m = target->arch_info;
breakpoint_t *breakpoint = NULL;
u32 resume_pc;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (!debug_execution)
{
target_free_all_working_areas(target);
cortex_m3_enable_breakpoints(target);
cortex_m3_enable_watchpoints(target);
}
-
+
if (debug_execution)
{
/* Disable interrupts */
/* We disable interrupts in the PRIMASK register instead of
masking with C_MASKINTS,
- * This is probably the same issue as Cortex-M3 Errata 377493:
+ * This is probably the same issue as Cortex-M3 Errata 377493:
* C_MASKINTS in parallel with disabled interrupts can cause
local faults to not be taken. */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value,
0, 32, 1);
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
/* Make sure we are in Thumb mode */
- buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
32,
+ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
32,
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
}
/* current = 1: continue on current pc, otherwise continue at <address>
*/
- if (!current)
+ if (!current)
{
buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32,
address);
armv7m->core_cache->reg_list[15].dirty = 1;
armv7m->core_cache->reg_list[15].valid = 1;
}
-
+
resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
armv7m_restore_context(target);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
@@ -669,10 +669,10 @@
cortex_m3_set_breakpoint(target, breakpoint);
}
}
-
+
/* Restart core */
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
-
+
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
@@ -689,7 +689,7 @@
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
}
-
+
return ERROR_OK;
}
@@ -711,25 +711,25 @@
/* current = 1: continue on current pc, otherwise continue at <address>
*/
if (!current)
buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32,
address);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target,
buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32))))
cortex_m3_unset_breakpoint(target, breakpoint);
-
+
target->debug_reason = DBG_REASON_SINGLESTEP;
-
+
armv7m_restore_context(target);
-
+
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-
+
/* set step and clear halt */
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
-
+
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
@@ -748,23 +748,23 @@
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int assert_srst = 1;
-
- LOG_DEBUG("target->state: %s",
+
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state
)->name );
-
+
if (!(jtag_reset_config & RESET_HAS_SRST))
{
LOG_ERROR("Can't assert SRST");
return ERROR_FAIL;
}
-
+
/* Enable debug requests */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
-
+
mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
-
+
if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
@@ -773,11 +773,11 @@
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
-
+
/* clear C_HALT in dhcsr reg */
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
-
- /* Enter debug state on reset, cf. end_reset_event() */
+
+ /* Enter debug state on reset, cf. end_reset_event() */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR |
VC_BUSERR);
}
else
@@ -785,18 +785,18 @@
/* Enter debug state on reset, cf. end_reset_event() */
mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR |
VC_BUSERR | VC_CORERESET);
}
-
+
/* following hack is to handle luminary reset
* when srst is asserted the luminary device seesm to also clear the
debug registers
* which does not match the armv7 debug TRM */
-
+
if (strcmp(target->variant, "lm3s") == 0)
{
/* get revision of lm3s target, only early silicon has this
issue
* Fury Rev B, DustDevil Rev B, Tempest all ok */
-
+
u32 did0;
-
+
if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
{
switch ((did0 >> 16) & 0xff)
@@ -805,7 +805,7 @@
/* all Sandstorm suffer issue */
assert_srst = 0;
break;
-
+
case 1:
case 3:
/* only Fury/DustDevil rev A suffer
reset problems */
@@ -815,7 +815,7 @@
}
}
}
-
+
if (assert_srst)
{
/* default to asserting srst */
@@ -841,10 +841,10 @@
mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
}
}
-
+
target->state = TARGET_RESET;
jtag_add_sleep(50000);
-
+
armv7m_invalidate_core_regs(target);
if (target->reset_halt)
@@ -853,25 +853,25 @@
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
-
+
return ERROR_OK;
}
int cortex_m3_deassert_reset(target_t *target)
-{
- LOG_DEBUG("target->state: %s",
+{
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state
)->name);
-
+
/* deassert reset lines */
jtag_add_reset(0, 0);
-
+
return ERROR_OK;
}
void cortex_m3_enable_breakpoints(struct target_s *target)
{
breakpoint_t *breakpoint = target->breakpoints;
-
+
/* set any pending breakpoints */
while (breakpoint)
{
@@ -886,11 +886,11 @@
int retval;
int fp_num=0;
u32 hilo;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
cortex_m3_fp_comparator_t * comparator_list =
cortex_m3->fp_comparator_list;
if (breakpoint->set)
@@ -898,7 +898,7 @@
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
-
+
if (cortex_m3->auto_bp_type)
{
breakpoint->type = (breakpoint->address < 0x20000000) ?
BKPT_HARD : BKPT_SOFT;
@@ -957,7 +957,7 @@
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
-
+
if (breakpoint->type == BKPT_HARD)
{
int fp_num = breakpoint->set - 1;
@@ -1005,7 +1005,7 @@
#ifdef ARMV7_GDB_HACKS
if (breakpoint->length != 2) {
/* XXX Hack: Replace all breakpoints with length != 2
with
- * a hardware breakpoint. */
+ * a hardware breakpoint. */
breakpoint->type = BKPT_HARD;
breakpoint->length = 2;
}
@@ -1035,11 +1035,11 @@
LOG_INFO("only breakpoints of two bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available--;
cortex_m3_set_breakpoint(target, breakpoint);
-
+
return ERROR_OK;
}
@@ -1048,13 +1048,13 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (cortex_m3->auto_bp_type)
{
breakpoint->type = (breakpoint->address < 0x20000000) ?
BKPT_HARD : BKPT_SOFT;
@@ -1064,10 +1064,10 @@
{
cortex_m3_unset_breakpoint(target, breakpoint);
}
-
+
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available++;
-
+
return ERROR_OK;
}
@@ -1075,7 +1075,7 @@
{
int dwt_num=0;
u32 mask, temp;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
@@ -1131,7 +1131,7 @@
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
cortex_m3_dwt_comparator_t * comparator_list =
cortex_m3->dwt_comparator_list;
int dwt_num;
-
+
if (!watchpoint->set)
{
LOG_WARNING("watchpoint not set");
@@ -1159,7 +1159,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
@@ -1170,14 +1170,14 @@
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
if ((watchpoint->length != 1) && (watchpoint->length != 2) &&
(watchpoint->length != 4))
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
cortex_m3->dwt_comp_available--;
-
+
return ERROR_OK;
}
@@ -1186,27 +1186,27 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (watchpoint->set)
{
cortex_m3_unset_watchpoint(target, watchpoint);
}
-
+
cortex_m3->dwt_comp_available++;
-
+
return ERROR_OK;
}
void cortex_m3_enable_watchpoints(struct target_s *target)
{
watchpoint_t *watchpoint = target->watchpoints;
-
+
/* set any pending watchpoints */
while (watchpoint)
{
@@ -1222,12 +1222,12 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
/* read a normal core register */
retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
-
+
if (retval != ERROR_OK)
{
LOG_ERROR("JTAG failure %i",retval);
@@ -1239,33 +1239,33 @@
{
/* read other registers */
cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
-
+
switch (num)
{
case 19:
*value = buf_get_u32((u8*)value, 0, 8);
break;
-
+
case 20:
*value = buf_get_u32((u8*)value, 8, 8);
break;
-
+
case 21:
*value = buf_get_u32((u8*)value, 16, 8);
break;
-
+
case 22:
*value = buf_get_u32((u8*)value, 24, 8);
break;
}
-
+
LOG_DEBUG("load from special reg %i value 0x%x", num, *value);
}
else
{
return ERROR_INVALID_ARGUMENTS;
}
-
+
return ERROR_OK;
}
@@ -1273,7 +1273,7 @@
{
int retval;
u32 reg;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
@@ -1284,11 +1284,11 @@
* hack to deal with the fact that gdb will sometimes "forge"
* return addresses, and doesn't set the LSB correctly (i.e., when
* printing expressions containing function calls, it sets LR=0.) */
-
+
if (num == 14)
value |= 0x01;
#endif
-
+
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
@@ -1303,38 +1303,38 @@
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core
register */
{
/* write other registers */
-
+
cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
-
+
switch (num)
{
case 19:
buf_set_u32((u8*)®, 0, 8, value);
break;
-
+
case 20:
buf_set_u32((u8*)®, 8, 8, value);
break;
-
+
case 21:
buf_set_u32((u8*)®, 16, 8, value);
break;
-
+
case 22:
buf_set_u32((u8*)®, 24, 8, value);
break;
}
-
+
cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
-
+
LOG_DEBUG("write special reg %i value 0x%x ", num, value);
}
else
{
return ERROR_INVALID_ARGUMENTS;
}
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32
count, u8 *buffer)
@@ -1343,13 +1343,13 @@
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
-
+
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) ||
!(buffer))
return ERROR_INVALID_ARGUMENTS;
-
+
/* cortex_m3 handles unaligned memory access */
-
+
switch (size)
{
case 4:
@@ -1365,7 +1365,7 @@
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
}
-
+
return retval;
}
@@ -1375,11 +1375,11 @@
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
-
+
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) ||
!(buffer))
return ERROR_INVALID_ARGUMENTS;
-
+
switch (size)
{
case 4:
@@ -1389,13 +1389,13 @@
retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count,
address);
break;
case 1:
- retval = mem_ap_write_buf_u8(swjdp, buffer, count,
address);
+ retval = mem_ap_write_buf_u8(swjdp, buffer, count,
address);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
}
-
+
return retval;
}
@@ -1420,27 +1420,33 @@
int retval;
u32 cpuid, fpcr, dwtcr, ictr;
int i;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
+ if (!cortex_m3->jtag_info.tap->enabled)
+ {
+ LOG_ERROR("Can not examine target %s, TAP not enabled yet",
target->type->name);
+ return ERROR_FAIL;
+ }
+
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
-
+
if (!target->type->examined)
{
target->type->examined = 1;
-
+
/* Read from Device Identification Registers */
if ((retval = target_read_u32(target, CPUID, &cpuid)) !=
ERROR_OK)
return retval;
-
+
if (((cpuid >> 4) & 0xc3f) == 0xc23)
LOG_DEBUG("CORTEX-M3 processor detected");
LOG_DEBUG("cpuid: 0x%8.8x", cpuid);
-
+
target_read_u32(target, NVIC_ICTR, &ictr);
cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4);
@@ -1449,7 +1455,7 @@
target_read_u32(target, NVIC_ISE0 + 4 * i,
cortex_m3->intsetenable + i);
LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i,
cortex_m3->intsetenable[i]);
}
-
+
/* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr);
cortex_m3->auto_bp_type = 1;
@@ -1464,7 +1470,7 @@
cortex_m3->fp_comparator_list[i].fpcr_address =
FP_COMP0 + 4 * i;
}
LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr,
cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
-
+
/* Setup DWT */
target_read_u32(target, DWT_CTRL, &dwtcr);
cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF;
@@ -1475,26 +1481,26 @@
cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i;
}
}
-
+
return ERROR_OK;
}
int cortex_m3_quit(void)
{
-
+
return ERROR_OK;
}
int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
{
u16 dcrdr;
-
+
mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (u8)dcrdr;
*value = (u8)(dcrdr >> 8);
-
+
LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
-
+
/* write ack back to software dcc register
* signify we have read data */
if (dcrdr & (1 << 0))
@@ -1502,7 +1508,7 @@
dcrdr = 0;
mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
}
-
+
return ERROR_OK;
}
@@ -1513,13 +1519,13 @@
u8 data;
u8 ctrl;
u32 i;
-
+
for (i = 0; i < (size * 4); i++)
{
cortex_m3_dcc_read(swjdp, &data, &ctrl);
buffer[i] = data;
}
-
+
return ERROR_OK;
}
@@ -1530,22 +1536,22 @@
return ERROR_OK;
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
if (!target->dbg_msg_enabled)
return ERROR_OK;
-
+
if (target->state == TARGET_RUNNING)
{
u8 data;
u8 ctrl;
-
+
cortex_m3_dcc_read(swjdp, &data, &ctrl);
-
+
/* check if we have data */
if (ctrl & (1 << 0))
{
u32 request;
-
+
/* we assume target is quick enough */
request = data;
cortex_m3_dcc_read(swjdp, &data, &ctrl);
@@ -1557,7 +1563,7 @@
target_request(target, request);
}
}
-
+
return ERROR_OK;
}
@@ -1569,14 +1575,14 @@
/* prepare JTAG information for the new target */
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
-
+
armv7m->swjdp_info.dp_select_value = -1;
armv7m->swjdp_info.ap_csw_value = -1;
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
/* initialize arch-specific breakpoint handling */
-
+
cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
cortex_m3->arch_info = NULL;
@@ -1585,26 +1591,26 @@
armv7m->pre_debug_entry = NULL;
armv7m->post_debug_entry = NULL;
-
+
armv7m->pre_restore_context = NULL;
armv7m->post_restore_context = NULL;
-
- armv7m_init_arch_info(target, armv7m);
+
+ armv7m_init_arch_info(target, armv7m);
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
-
+
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1,
target);
-
+
return ERROR_OK;
}
int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
{
cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
-
+
cortex_m3_init_arch_info(target, cortex_m3, target->tap);
-
+
return ERROR_OK;
}
@@ -1612,12 +1618,12 @@
{
int retval;
command_t *cortex_m3_cmd;
-
+
retval = armv7m_register_commands(cmd_ctx);
-
- cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL,
COMMAND_ANY, "cortex_m3 specific commands");
+
+ cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL,
COMMAND_ANY, "cortex_m3 specific commands");
register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3
interrupts ['on'|'off']");
-
+
return retval;
}
@@ -1626,13 +1632,13 @@
target_t *target = get_current_target(cmd_ctx);
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\"
command", cmd);
return ERROR_OK;
}
-
+
if (argc > 0)
{
if (!strcmp(args[0], "on"))
@@ -1648,9 +1654,9 @@
command_print(cmd_ctx, "usage: cortex_m3 maskisr
['on'|'off']");
}
}
-
+
command_print(cmd_ctx, "cortex_m3 interrupt mask %s",
(cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
-
+
return ERROR_OK;
}
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