Spencer Oliver wrote: >> We have an STR712 board by Olimex but (actually, an IAR >> kickstart board). We can do the "halt reset" with no errors >> but it does not do a clean reset (the PC does not go to >> zero). With soft_reset_halt it does go back to zero. There >> are no errors logged in either case. >> soft_reset_halt just gives a cleaner reset. >> >> However, halt reset gives a clean reset with STM32 boards and >> I use it for them. >> >> Also, when we put in the reset_config ... shown above the >> debug session becomes non-functional but no openocd errors are logged. >> >> -gene > > Because the str7 has the srst and trst tied internally a reset halt will > never halt @ 0. > A reset halt on this device will always be a 'reset run' then 'halt' command > - > so a few instructions will always be executed.
Exactly! We see it reset then gets to some application code that prints to the uart then stops. > > This is why people often put a small reset delay in the startup file for the > str7 to compensate for this. Last I checked there was a str710.cfg file which we use. How do you set his "small reset delay" you speak of? Would this be jtag_n[st]rst_delay? Should this be in str710.cfg? > Other cores such as stm32 or str9 will reset correctly @ 0 when a 'reset > halt' is issued. > > Cheers > Spen _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
