Hi Stefano,
I think, I have the same problem...
I have a MMnet1001 module from Propox. This module has a AT91SAM9260
chip. This chip has an ARM926EJ-S Processor.
I am using the Amontec Chameleon dongle, loaded with the JTAG
Accelerator configuration. (RTCK-feature enabled)
When commanding the module "reset halt", the halt times out and the
module is still running.
In the software there are 2 ways to halt the module after a reset:
vector catching and breakpoints.
The software uses vector catch and that doesn't work in my setup (halt
times out).
When I force it to use breakpoints, it works fine in my setup!
It looks like the vector catching is not working properly.
Attached is the patch that works for me.
It is not intended to be committed into the project, because it disables
the vector catch for all arm7/9 targets during reset.
Index: src/target/arm7_9_common.c
===================================================================
--- src/target/arm7_9_common.c (revision 2564)
+++ src/target/arm7_9_common.c (working copy)
@@ -1002,6 +1002,13 @@
return ERROR_FAIL;
}
+ LOG_INFO("<<arm7_9_assert_reset>> halt=%d, vector_catch=%d,
has_srst=%d, srst_pulls_trst=%d",
+ target->reset_halt,
+ arm7_9->has_vector_catch,
+ jtag_reset_config & RESET_HAS_SRST,
+ jtag_reset_config & RESET_SRST_PULLS_TRST
+ );
+
if (target->reset_halt)
{
/*
@@ -1011,7 +1018,7 @@
* If TRST is asserted, then these settings will be reset
anyway, so setting them
* here is harmless.
*/
- if (arm7_9->has_vector_catch)
+ if (0 && arm7_9->has_vector_catch)
{
/* program vector catch register to catch reset vector
*/
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
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