I found a solution to my problem. It seems that this module needs one
clock cycle in state RUN TEST/IDLE between the setting of the vector
catch and the reset. Then it works perfectly. I tested it with the
RTCK-feature and on 1 kHz, 2 kHz and 4 kHz. It didn't work at 8kHz,
because the chip clock falls back to 32 kHz at reset. I have attached a
patch file to include the extra cycle in state RUN TEST/IDLE.
Ferdinand Postema schreef:
Hi Stefano,
I think, I have the same problem...
I have a MMnet1001 module from Propox. This module has a AT91SAM9260
chip. This chip has an ARM926EJ-S Processor.
I am using the Amontec Chameleon dongle, loaded with the JTAG
Accelerator configuration. (RTCK-feature enabled)
When commanding the module "reset halt", the halt times out and the
module is still running.
In the software there are 2 ways to halt the module after a reset:
vector catching and breakpoints.
The software uses vector catch and that doesn't work in my setup (halt
times out).
When I force it to use breakpoints, it works fine in my setup!
It looks like the vector catching is not working properly.
Attached is the patch that works for me.
It is not intended to be committed into the project, because it
disables the vector catch for all arm7/9 targets during reset.
Index: src/target/arm7_9_common.c
===================================================================
--- src/target/arm7_9_common.c (revision 2571)
+++ src/target/arm7_9_common.c (working copy)
@@ -1015,6 +1015,7 @@
{
/* program vector catch register to catch reset vector
*/
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+ jtag_add_runtest(1, jtag_get_end_state());
}
else
{
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