> I found a solution to my problem. It seems that this module > needs one clock cycle in state RUN TEST/IDLE between the > setting of the vector catch and the reset. Then it works > perfectly. I tested it with the RTCK-feature and on 1 kHz, 2 > kHz and 4 kHz. It didn't work at 8kHz, because the chip clock > falls back to 32 kHz at reset. I have attached a patch file > to include the extra cycle in state RUN TEST/IDLE. > > Ferdinand Postema schreef: > > Hi Stefano, > > > > I think, I have the same problem... > > I have a MMnet1001 module from Propox. This module has a > AT91SAM9260 > > chip. This chip has an ARM926EJ-S Processor. > > I am using the Amontec Chameleon dongle, loaded with the JTAG > > Accelerator configuration. (RTCK-feature enabled) > >
committed thanks, this also fixes the issues i was seeing on a str9. Cheers Spen _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
