Hi all,
This series patches fix the hardware single-step logic mainly.
With these patches, you can do the step operation on the telnet session.
Also, the programming breakpoints works as well.
Cheers,
Matt
>From 8fc6c1839b80447e06c368b0d8948f5feda3e474 Mon Sep 17 00:00:00 2001
From: Matt Hsu <[email protected]>
Date: Thu, 3 Sep 2009 21:21:02 +0800
Subject: [PATCH 1/3] [Cortex_A8] Add Bit-offset for DSCR
Signed-off-by: Matt Hsu <[email protected]>
---
src/target/cortex_a8.h | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index bb57b13..a1efe66 100644
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -67,6 +67,15 @@ extern char* cortex_a8_state_strings[];
#define BRP_NORMAL 0
#define BRP_CONTEXT 1
+/* DSCR Bit offset */
+#define DSCR_CORE_HALTED 0
+#define DSCR_CORE_RESTARTED 1
+#define DSCR_EXT_INT_EN 13
+#define DSCR_HALT_DBG_MODE 14
+#define DSCR_MON_DBG_MODE 15
+#define DSCR_INSTR_COMP 24
+#define DSCR_DTR_TX_FULL 29
+
typedef struct cortex_a8_brp_s
{
int used;
--
1.6.0.4
>From 2b8c724c79378440ec1cd37aa221453565b934c1 Mon Sep 17 00:00:00 2001
From: Matt Hsu <[email protected]>
Date: Thu, 3 Sep 2009 21:29:35 +0800
Subject: [PATCH 2/3] [Cortex_A8] Fix step/breakpoint logic
The breakpoints could be generated by enabling halting debug mode.
This patch also fixes hardware step, since signle-stepping is implemented by
allocating mismatch breakpoint.
Signed-off-by: Matt Hsu <[email protected]>
---
src/target/cortex_a8.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 829bf3d..948536a 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -430,6 +430,13 @@ int cortex_a8_halt(target_t *target)
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
+ /*
+ * enter halting debug mode
+ */
+ mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_write_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+
if (retval != ERROR_OK)
goto out;
--
1.6.0.4
>From a12b910299e740a0b8c1847ed883c24b284a4931 Mon Sep 17 00:00:00 2001
From: Matt Hsu <[email protected]>
Date: Thu, 3 Sep 2009 21:35:43 +0800
Subject: [PATCH 3/3] [Cortex_A8] Tidy up the bit-offset operation for DSCR register
Signed-off-by: Matt Hsu <[email protected]>
---
src/target/cortex_a8.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 948536a..5fa3103 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -166,7 +166,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
retvalue = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
@@ -175,7 +175,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
retvalue = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
return retvalue;
}
@@ -291,7 +291,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+ while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -443,7 +443,7 @@ int cortex_a8_halt(target_t *target)
do {
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << 0)) == 0);
+ } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
target->debug_reason = DBG_REASON_DBGRQ;
@@ -542,7 +542,7 @@ int cortex_a8_resume(struct target_s *target, int current,
do {
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << 1)) == 0);
+ } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
@@ -589,7 +589,7 @@ int cortex_a8_debug_entry(target_t *target)
/* Enable the ITR execution once we are in debug mode */
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- dscr |= (1 << 13);
+ dscr |= (1 << DSCR_EXT_INT_EN);
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
--
1.6.0.4
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