> The FPGA isn't that difficult. I've created a similar setup using > OpenOCD. The biggest problem I had was that OpenOCD is spending most of > its time creating JTAG bit streams. Its not the bit-banging that takes > most of the time! On a 333MHz platform it took about 15 minutes to > program 180kB into flash (with an FPGA for the JTAG interface!). > > To get more speed I created pre-defined JTAG commands for memory write > and memory read and fill in the blanks (address and data) when necessary > (very target specific ofcourse!). This reduced the programming time to a > few seconds. I guess the effect will be less on a PC, but I think it > might be worth to do some profiling. This could be made into a generic > solution if OpenOCD would support a caching mechanism that allows > patching existing JTAG bit streams.
If you have a low latency system embedded system, then you will get the best performance by implementing a minidriver. You can then e.g. implement a hardware FIFO for JTAG commands(zy1000 does this). With a hardware fifo all jtag_add_xxx() calls are then synchronous which saves *lots* of copying, etc. ZY1000 gets 400kBytes/s speeds w/an arm7 CPU running eCos. There's some documentation on minidrivers in openocd, but if you are doing this for commercial reasons, then perhaps you would like to contact Zylin to get a finished(or customizable by you/us) solution? ;-) -- Øyvind Harboe http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
