On Tuesday 16 February 2010 12:11:42 Øyvind Harboe wrote: > On Tue, Feb 16, 2010 at 12:06 PM, Marc Pignat <[email protected]> wrote: > > On Tuesday 16 February 2010 11:45:36 Øyvind Harboe wrote: ... > We're late in the 0.4 release cycle, so we'll have to have the release > managers approval for that.
What about a minimalistic bugfix like this? Subject: arm920t data cache flush is broken According to the arm920t TRM (ARM DDI 0151C), only a small subset of cp15 operations are supported through the jtag (see 9.6.7 Scan chains 4 and 15, the ARM920T memory system). The 'MCR p15,0,Rd,c7,c10,2' (Flush and invalidate data cache using MVA) instruction is not supported (== unpredictable behavior). The current code uses this opcode and apparently it does nothing (no flush, no invalidate), and this will cause data corruption. Here is a patch using 'MCR p15,0,Rd,c7,c10,2' (Invalidate data cache using MVA), that fixes the bug when using data cache in write through mode. Signed-off-by: Marc Pignat <[email protected]> diff --git a/src/target/arm920t.c b/src/target/arm920t.c index e04d9fc..d60ea2b 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -538,8 +538,14 @@ int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { LOG_DEBUG("D-Cache enabled, flush and invalidate cache line"); - /* MCR p15,0,Rd,c7,c10,2 */ - retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address); + /* + * MCR p15,0,Rd,c7,c6,1 - Invalidate DCache single entry using MVA + * + * FIXME : Clean and Invalidate instruction is not + * available in intepreted mode, so cache in write back + * mode will most likely become inconsistent. + */ + retval = arm920t_write_cp15_interpreted(target, 0xee070f36, 0x0, address&~0x3); if (retval != ERROR_OK) return retval; } _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
