On Tue, Feb 16, 2010 at 11:31 PM, David Brownell <[email protected]> wrote: > On Tuesday 16 February 2010, Marc Pignat wrote: >> If I understand the arm920t TRM well, there is no way to flush something >> using >> the JTAG interface (only invalidate),so support for data cache in write back >> mode will be difficult. > > Not using scanchain 15 operations, no. > > But I don't think there's any particular reason the generic ARM9 > "execute this instruction" logic wouldn't be able to execute those > opcodes. It's a bit more trouble -- you'd have to stuff some > register with the MVA of the line to flush, and (easy) make sure > that register is properly restored later. > > Another option of course is to > > - first invalidate the line(s) you'll be writing
This will break things as the cache line can already contain stuff should be flushed, i.e. that you need to modify *part* of the cache line. Marc's patch solves this by reading a cache line from memory, writing it to physical memory, then invalidating the cache line. Very straightforward and readable using only existing and tested bits and bobs. -- Øyvind Harboe Visit us at Embedded World, March 2nd-4th. IS2T's stand, HALL 10 - 118 http://www.zylin.com/events_embeddedworld.html US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
