> If I understand the arm920t TRM well, there is no way to flush something using > the JTAG interface (only invalidate),so support for data cache in write back > mode will be difficult. > > I see some solutions: > 1) execute the code on the target (clean and invalidate data cache) > * This solution will probably call the function we're fixing, (The chicken > or the egg?)
You just pointed out why this is probably a dead end... > 2) Do it by hand (Manually flush the data cache) > * Read the whole data cache line in openocd > * invalidate this data cache line > * invalidate this instruction cache line > * write the whole cache line from openocd to the physical memory To implement a flush using: - read data in cache line. This can be done via JTAG, right? We even have code to do so? - write to physical memory - invalidate cache line I think we have the bits and bobs in the arm920t code to this... > > 3) Be smart > a) Write to the physical address > b) invalidate icache > c) Write to the virtual address > d) Invalidate data cache only if c has failed (it has failed because it is > read-only and so the line can't be dirty -> no problem with > write-back). > + I'm not sure risking a mmu exception is so smart... Doesn't work/too clever? Also we invalidate cache lines, which involve *more* than the data we are trying to write through the cache + memory... > Which is the best way to take? I don't know. :-) -- Øyvind Harboe Visit us at Embedded World, March 2nd-4th. IS2T's stand, HALL 10 - 118 http://www.zylin.com/events_embeddedworld.html US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
