Hi folks,
I am trying to get OpenOCD 0.4.0 (built from git) working with an Amontek
JTAGKey-Tiny. I am using a home-made adapter to TI 14-pin JTAG header which has
TRST but no SRST, on our board which features Texas DM355 and one other chip in
the scan chain (which I don't care much about). For info we have been using the
Ronetix PEEDI JTAG programmer through the same connector successfully on this
board and other copies, so the design and connector are known to work.
I used OpenOCD a little a couple of years ago and it's clearly come on a long
way - I'm keen to play with the NAND flash support.
I have copied dm355evm.cfg and customised with a couple of lines like:
jtag newtap penta tap -irlen 5 -expected-id 0x04040009
# paranoia / trying to make stuff work:
jtag_rclk 100
reset_config trst_only separate
I can talk to the board a little, but I think I need to configure OpenOCD with
a software reset or something to replace the missing SRST?
On starting OpenOCD with the hardware powered up (sitting at the u-boot prompt)
I get this output:
Open On-Chip Debugger 0.4.0 (2010-04-13-14:08)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
RCLK - adaptive
fast memory access is enabled
dcc downloads are enabled
RCLK - adaptive
trst_only separate trst_push_pull
Info : RCLK (adaptive clock speed) not supported - fallback to 100 kHz
Info : JTAG tap: penta.tap tap/device found: 0x04040009 (mfg: 0x004, part:
0x4040, ver: 0x0)
Info : JTAG tap: dm355.jrc tap/device found: 0x0b73b02f (mfg: 0x017, part:
0xb73b, ver: 0x0)
Warn : Unexpected idcode after end of chain: 64 0x800000ff
Warn : Unexpected idcode after end of chain: 96 0x0000007f
Error: double-check your JTAG setup (interface, speed, missing TAPs, ...)
Info : JTAG tap: penta.tap tap/device found: 0x04040009 (mfg: 0x004, part:
0x4040, ver: 0x0)
Info : JTAG tap: dm355.jrc tap/device found: 0x0b73b02f (mfg: 0x017, part:
0xb73b, ver: 0x0)
Info : JTAG tap: dm355.etb enabled
Info : JTAG tap: dm355.arm enabled
Info : Embedded ICE version 6
Info : dm355.arm: hardware has 2 breakpoint/watchpoint units
Info : ETM v1.3
I can telnet in and do "halt", "resume", "step", "soft_reset_halt":
> soft_reset_halt
requesting target halt and executing a soft reset
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x800000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> step
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x800000d3 pc: 0x00008000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
But "reset halt" complains it does not know how to reset:
> reset halt
RCLK not supported - fallback to 1500 kHz
JTAG tap: penta.tap tap/device found: 0x04040009 (mfg: 0x004, part: 0x4040,
ver: 0x0)
JTAG tap: dm355.jrc tap/device found: 0x0b73b02f (mfg: 0x017, part: 0xb73b,
ver: 0x0)
JTAG tap: dm355.etb enabled
JTAG tap: dm355.arm enabled
dm355.arm: how to reset?
Command handler execution failed
in procedure 'reset' called at file "command.c", line 650
called at file "command.c", line 361
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x400000d3 pc: 0x81084598
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Although sometimes "reset halt" fails - perhaps because the clock rate gets
reset too high?:
> reset halt
RCLK not supported - fallback to 1500 kHz
JTAG tap: penta.tap tap/device found: 0x82020009 (mfg: 0x004, part: 0x2020,
ver: 0x8)
JTAG tap: penta.tap UNEXPECTED: 0x82020009 (mfg: 0x004, part: 0x2020,
ver: 0x8)
JTAG tap: penta.tap expected 1 of 1: 0x04040009 (mfg: 0x004, part: 0x4040,
ver: 0x0)
JTAG tap: dm355.jrc tap/device found: 0x0b73d817 (mfg: 0x40b, part: 0xb73d,
ver: 0x0)
JTAG tap: dm355.jrc UNEXPECTED: 0x0b73d817 (mfg: 0x40b, part: 0xb73d,
ver: 0x0)
JTAG tap: dm355.jrc expected 1 of 1: 0x0b73b02f (mfg: 0x017, part: 0xb73b,
ver: 0x0)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
Also, If I leave the board powered and halted, I get this happen after a few
minutes:
WARNING: unknown debug reason: 0xf
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x400000d3 pc: 0x81084548
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Or sometimes:
WARNING: unknown debug reason: 0xe
invalid mode value encountered 0
cpsr contains invalid mode value - communication failure
WARNING: unknown debug reason: 0xe
cp15 read operation timed out
cp15 read operation timed out
cp15 read operation timed out
cp15 read operation timed out
cp15 read operation timed out
cp15 write operation timed out
target state: halted
target halted in Thumb state due to debug-request, current mode: User
cpsr: 0x00008f30 pc: 0xfffffffa
MMU: enabled, D-Cache: enabled, I-Cache: disabled
While this is happening the server console sometimes prints:
Jazelle debug entry -- BROKEN!
invalid mode value encountered 0
Jazelle state handling is BROKEN!
What is these? watchdog resets?
Thanks,
--
Jon Povey
[email protected]
Racelogic is a limited company registered in England. Registered number 2743719
.
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks,
MK18 1TB .
The information contained in this electronic mail transmission is intended by
Racelogic Ltd for the use of the named individual or entity to which it is
directed and may contain information that is confidential or privileged. If you
have received this electronic mail transmission in error, please delete it from
your system without copying or forwarding it, and notify the sender of the
error by reply email so that the sender's address records can be corrected. The
views expressed by the sender of this communication do not necessarily
represent those of Racelogic Ltd. Please note that Racelogic reserves the right
to monitor e-mail communications passing through its network
_______________________________________________
Openocd-development mailing list
[email protected]
https://lists.berlios.de/mailman/listinfo/openocd-development
