Hi Laurent, thanks for the reply. Laurent Gauch wrote: > Could you please let us know if you have selected ICE Pick or ARM > debug mode from the EMU0 and EMU1 ? > note: ICE Pick Mode may have an issue booting from Reset ! > > For ARM Mode please configure your jumper for EMU0 = '0' and EMU1 = > '0' (pulldown 2.2k or smaller).
EMU0 and EMU1 are routed to the JTAG header but no other pulls or jumpers on this board, so just the internal DM355 pullup - they will both be "1". The OpenOCD script seems to be enabling the other TAPs via the ICE though.. Not sure what you mean by ICE Pick Mode having issues booting from reset? > note : you could still route the SRST (ARM RESET signal) from the > Amontec JTAGkey-Tiny to the ARM_RSTn signal on your DM355 board. (eg. > on pin 15 of the TI SAMTEC 20-pin header). I might have to try that later. This is a custom board without the 20-pin header, I can get at RESET on a test point or something if I have to. At the moment I am looking into triggering a watchdog reset with a reset-assert handler.. Be good if I can avoid soldering. > If you want to use the RTCK (adaptive return clock ) signal, you could > update your ICE to an Amontec JTAGkey-2 dongle. This will help > accelerate your debug and help to have a stable debug. If I can get this stuff working we may order a few :) -- Jon Povey [email protected] Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
