Hi Drasko,
I proposed a solution for the MIPS big-endian problem in the past. See
https://lists.berlios.de/pipermail/openocd-development/2009-June/008659.html
The FASTDATA patch was accepted later and included the
mips_m4k_bulk_write_memory() function that corrects for big-endian targets.
https://lists.berlios.de/pipermail/openocd-development/2009-September/010308.html
mips_m4k_bulk_write_memory was designed to write large files to RAM. I use it to
load RAM boot loaders. The value of 128 is arbitrarily large compared to the mww
command.
Without the patch below, mww and mdw do not work and my DDR setup also fails.
With the patch it works.
- David
src/target/mips_m4k.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 8afee9c..965f326 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -864,6 +864,28 @@ static int mips_m4k_read_memory(struct target *target,
uint32_t address,
if (ERROR_OK != retval)
return retval;
+ /* TAP data register is loaded LSB first (little endian) */
+ if (target->endianness == TARGET_BIG_ENDIAN)
+ {
+ uint32_t i, t32;
+ uint16_t t16;
+
+ for (i = 0; i < (count * size); i += size)
+ {
+ switch (size)
+ {
+ case 4:
+ t32 = le_to_h_u32(&buffer[i]);
+ h_u32_to_be(&buffer[i], t32);
+ break;
+ case 2:
+ t16 = le_to_h_u16(&buffer[i]);
+ h_u16_to_be(&buffer[i], t16);
+ break;
+ }
+ }
+ }
+
return ERROR_OK;
}
@@ -889,6 +911,28 @@ static int mips_m4k_write_memory(struct target *target,
uint32_t address,
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address &
0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
+ /* TAP data register is loaded LSB first (little endian) */
+ if (target->endianness == TARGET_BIG_ENDIAN)
+ {
+ uint32_t i, t32;
+ uint16_t t16;
+
+ for (i = 0; i < (count*size); i += size)
+ {
+ switch (size)
+ {
+ case 4:
+ t32 = be_to_h_u32(&buffer[i]);
+ h_u32_to_le(&buffer[i], t32);
+ break;
+ case 2:
+ t16 = be_to_h_u16(&buffer[i]);
+ h_u16_to_le(&buffer[i], t16);
+ break;
+ }
+ }
+ }
+
/* if noDMA off, use DMAACC mode for memory write */
if (ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_write_mem(ejtag_info, address, size, count,
(void *)buffer);
On 03/17/2011 08:45 AM, Drasko DRASKOVIC wrote:
Hi all,
I have few questions regarding MIPS and endianess :
1) In openocd/src/target/mips_m4k.c we can see that target endianess
is checked and treated only mips_m4k_bulk_write_memory() in and not
mips_m4k_write_memory() and mips_m4k_read_memory(). Why is this so ?
(It leads to wrong SDRAM setup, as mww and mdw commands make no sense
in my case, because mips_m4k_write_memory() is called and my taget is
big endian).
2) When is mips_m4k_bulk_write_memory() actually called ? Obviously
from my tests - not always. I can see it called when I am trying to
load bigger files into SDRAM, but for smaller directly
mips_m4k_write_memory() is called (and thus endianess is never
treated). How does this fast_write actually works in MIPS case ?
3) Can we conclude based on this that big endian targets for MIMPS are
not supported in the current OpenOCD implementation ? Did anyone had
sucess running OpenOCD eith big endian target and how is it done in
this case, having in mind problems I pointed out.
Best regards,
Drasko
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