On Thu, Mar 17, 2011 at 10:19 PM, David Claffey <[email protected]> wrote:
> Hi Drasko,
>
> I proposed a solution for the MIPS big-endian problem in the past. See
> https://lists.berlios.de/pipermail/openocd-development/2009-June/008659.html
>
> The FASTDATA patch was accepted later and included the
> mips_m4k_bulk_write_memory() function that corrects for big-endian targets.
> https://lists.berlios.de/pipermail/openocd-development/2009-September/010308.html
Hi David,
thanks for these clarifications, as I run previously onto your patch
and I I was wondering why some pieces were integrated and other not...
> mips_m4k_bulk_write_memory was designed to write large files to RAM. I use
> it to load RAM boot loaders. The value of 128 is arbitrarily large compared
> to the mww command.
What I want to do is the similar thing - to load the images into the
RAM. Actually, load everything - in general : write RAM addresses.
Currently there seems to be limitation that the file must be greater
than 128 bytes so that mips_m4k_bulk_write_memory() is called,
ohterwise it will not work because endianess problem is still present
in mips_m4k_write_memory() (which is by the way inconsistent and
confusing).
>
> Without the patch below, mww and mdw do not work and my DDR setup also
> fails. With the patch it works.
Thanks for this information also, because this confirms what I have
been experiencing - when I integrated your changes from previous
patches (which is basically what you re-sent below) my SDRAM
initialization started to work and I was able to write and execute
small files. However, when I tried to load an eCos image, I noticed a
problem.
It should be noted however that this patch can not be applied on dev
branch as is, because if we move endianess treatement into simple read
and write functions, it should be removed from the
mips_m4k_bulk_write_memory() in the cases when fast_write is anawailbe
and it falls back to simple write (otherwise bytes will be shuffled
two times, once in the mips_m4k_bulk_write_memory() and then again in
mips_m4k_write_memory() ).
I will continue the investigation and keep you informed of results.
BR,
Drasko
>
> - David
>
> src/target/mips_m4k.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 44 insertions(+), 0 deletions(-)
>
> diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
> index 8afee9c..965f326 100644
> --- a/src/target/mips_m4k.c
> +++ b/src/target/mips_m4k.c
> @@ -864,6 +864,28 @@ static int mips_m4k_read_memory(struct target *target,
> uint32_t address,
> if (ERROR_OK != retval)
> return retval;
>
> + /* TAP data register is loaded LSB first (little endian) */
> + if (target->endianness == TARGET_BIG_ENDIAN)
> + {
> + uint32_t i, t32;
> + uint16_t t16;
> +
> + for (i = 0; i < (count * size); i += size)
> + {
> + switch (size)
> + {
> + case 4:
> + t32 = le_to_h_u32(&buffer[i]);
> + h_u32_to_be(&buffer[i], t32);
> + break;
> + case 2:
> + t16 = le_to_h_u16(&buffer[i]);
> + h_u16_to_be(&buffer[i], t16);
> + break;
> + }
> + }
> + }
> +
> return ERROR_OK;
> }
>
> @@ -889,6 +911,28 @@ static int mips_m4k_write_memory(struct target *target,
> uint32_t address,
> if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address &
> 0x1u)))
> return ERROR_TARGET_UNALIGNED_ACCESS;
>
> + /* TAP data register is loaded LSB first (little endian) */
> + if (target->endianness == TARGET_BIG_ENDIAN)
> + {
> + uint32_t i, t32;
> + uint16_t t16;
> +
> + for (i = 0; i < (count*size); i += size)
> + {
> + switch (size)
> + {
> + case 4:
> + t32 = be_to_h_u32(&buffer[i]);
> + h_u32_to_le(&buffer[i], t32);
> + break;
> + case 2:
> + t16 = be_to_h_u16(&buffer[i]);
> + h_u16_to_le(&buffer[i], t16);
> + break;
> + }
> + }
> + }
> +
> /* if noDMA off, use DMAACC mode for memory write */
> if (ejtag_info->impcode & EJTAG_IMP_NODMA)
> return mips32_pracc_write_mem(ejtag_info, address, size,
> count, (void *)buffer);
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