On Mon, Dec 19, 2011 at 9:34 PM, Matthew Hicks <[email protected]> wrote:
> Why do the instruction and data cache configuration registers contain the
> following fields, when earlier parts of the specification does not state
> that their associated registers are optional?
Can you indicate which bits of the spec you're talking about here?
The lack of something earlier in the spec saying they're optional does
not mean they're not optional.
>
> CCRI - cache control register implemented
> CBIRI - cache block invalidate register implemented
> CBFRI - cache block flush register implemented
> CBWBRI - cache block write back register implemented
>
> I recommend that these fields are removed from ICCFGR and DCCFGR.
>
Certainly the invalidate, flush and write-back registers are good to
have indicated as present. Different cache control algorithms may be
implemented and chosen at runtime depending on these bits.
Julius
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