On 04/21/2012 04:30 PM, Julius Baxter wrote:
On Fri, Dec 23, 2011 at 6:06 PM, Matthew Hicks<[email protected]> wrote:
Bug submitted.
OK, it took a while to get round to it but I've proposed a fix for
this problem in marking all the cache control registers with bits in
the I/DCCFGR as optional in the spec.
The only thing I'm not sure about here is whether the block invalidate
register should be optional or not. Is there any way we can live
without it? It sort of needs to be there for boot up, right? The
alternative is to mark that as not optional and remove its bit from
the I/DCCFGRs.
What do we say?
For the boot-up, the cache could invalidate itself on reset.
I don't see how we could live without it anyway though,
how would you be able to invalidate the cache without it?
Stefan
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