On 12/20/2011 09:10 PM, Matthew Hicks wrote:
On Tue, Dec 20, 2011 at 8:58 AM, Julius Baxter <[email protected] <mailto:[email protected]>> wrote:On Mon, Dec 19, 2011 at 9:34 PM, Matthew Hicks <[email protected] <mailto:[email protected]>> wrote: > Why do the instruction and data cache configuration registers contain the > following fields, when earlier parts of the specification does not state > that their associated registers are optional? Can you indicate which bits of the spec you're talking about here? The lack of something earlier in the spec saying they're optional does not mean they're not optional. I am referring to section 9.2 vs section 15.7/8 of the July 5th draft.It seems odd that the label "optional" would be applied to some of the cache registers but not to all that are considered optional. I think it would benefit the everyone if the manual consistently used tags like optional as opposed to using them in a pseudo-random fashion.
I agree, it is indeed a bit confusing the way it is presented now Stefan
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