The current options for locations of the exception vectors are not very flexible, the only two possible locations are at address 0x0 or address 0xf0000000.
I would like to propose an addition of an (optional) SPR register (EVBA) in group 0 (System Control and Status registers) at address 1536 (right after the last possible GPR mapped into SPR space), which would hold the (upper part of the) base address of the exception vectors. Comments? Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
