On Sun, Jan 29, 2012 at 10:09 PM, Stefan Kristiansson <[email protected]> wrote: > The current options for locations of the exception vectors > are not very flexible, the only two possible locations are at > address 0x0 or address 0xf0000000. > > I would like to propose an addition of an (optional) SPR register (EVBA) > in group 0 (System Control and Status registers) at address 1536 > (right after the last possible GPR mapped into SPR space), > which would hold the (upper part of the) base address of the exception > vectors. >
Hi Stefan Sounds fine. Can you go and flesh out this section on the wiki on this: http://opencores.org/or1k/Architecture_Specification#Exception_Vector_Base_Address Basically write up what you think the section should look like in the manual. Can you address some questions I have: * How wide will it be (how many bits of the address will it hold?) * Where is the presence bit going to be? * Will there be an enable bit somewhere to control whether this register is obeyed or not? (ie. will it be a synthesis-time or run-time option?) * Is SR[EPH] ignored when this system is in use? Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
