On Thu, Apr 12, 2012 at 05:40:21AM +0100, Julius Baxter wrote: > The following should implement and test the correct behaviour of the > delay slot execption bit in the supervisor register in the OR1200. > > > Index: rtl/verilog/or1200/or1200_except.v > =================================================================== > --- rtl/verilog/or1200/or1200_except.v (revision 787) > +++ rtl/verilog/or1200/or1200_except.v (working copy) > @@ -78,7 +78,8 @@ > except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc, > spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, > du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr, > - abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, > fpcsr_fpee > + abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, > fpcsr_fpee,
You probably want to turn off your e-mail clients line-wrapping function when pasting patches. > + dsx > > ); > > @@ -147,7 +148,8 @@ > input icpu_err_i; > input dcpu_ack_i; > input dcpu_err_i; Acked-by: Stefan Kristiansson <[email protected]> Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
