On Thu, Apr 12, 2012 at 8:37 AM, Jeremy Bennett
<[email protected]> wrote:
> On Thu, 2012-04-12 at 05:40 +0100, Julius Baxter wrote:
>> The following should implement and test the correct behaviour of the
>> delay slot execption bit in the supervisor register in the OR1200.
>
> Hi Julius,
>
> Good work. Would you add the test to the Or1ksim tests as well.
>
Hi Jeremy,
The trailing patch was all that was needed to get the software passing
in or1ksim too.
Amazingly simple. Surprised it'd never been implemented before.
Cheers
Julius
Index: cpu/or1k/except.c
===================================================================
--- cpu/or1k/except.c (revision 793)
+++ cpu/or1k/except.c (working copy)
@@ -74,6 +74,12 @@
/* Address translation is always disabled when starting exception. */
cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;
+ /* Set SR[DSX] if we're in delay slot */
+ if (cpu_state.delay_insn)
+ cpu_state.sprs[SPR_SR] |= SPR_SR_DSX;
+ else
+ cpu_state.sprs[SPR_SR] &= ~SPR_SR_DSX;
+
switch (except)
{
/* EPCR is irrelevent */
_______________________________________________
OpenRISC mailing list
[email protected]
http://lists.openrisc.net/listinfo/openrisc
