Hi guys, So I've been working on a variation of OpenRISC that doesn't have a branch delay slot.
One thing I've looked at is the way the OR1200 handles the PC, vs. the way a pipeline like MIPS does it. The biggest difference between the two is that OpenRISC jump offsets are all against the PC, while on MIPS the offset is against the PC+4. Doing it either way is fine, but it makes me wonder if the OpenRISC uses the non-incremented PC in order maybe to avoid a patent held by MIPS. Does anyone know? Also, some interesting things can be done with the PC when the delay slot is removed, things that make me want to use PC+4 for jump offsets. The most interesting thing is that, for instance, for l.jal instructions, no separate adder is needed to add 4 to the PC before it is written to the link register. However, I think the original PC might still be needed for exceptions, so it would still need to be passed down the pipeline. So real the question is whether it's better to pass the PC *and* the PC+4 down the pipeline, or just to add 4 to the PC at the stage its needed. (I suspect the latter, and this is what the OR1200 does.) Anyone have any ideas? -Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
