On Tue, Apr 17, 2012 at 9:23 AM, Jeremy Bennett <[email protected]> wrote: > On Mon, 2012-04-16 at 16:16 +0200, Peter Gavin wrote: >> Hi guys, >> >> So I've been working on a variation of OpenRISC that doesn't have a >> branch delay slot.
Hi Pete - what do you mean by this? do you mean RTL or compiler or software or everything? > > Hi Pete, > > Branch delays are definitely out of fashion. RISC-1 introduced them, but > we now know how to avoid them in hardware. Your variant would strictly > speaking not meet the OpenRISC 1000 architecture definition (it mandates > branch delay). Perhaps the architecture spec should be updated to make > branch delay optional. Agreed, any future architectures will not have delay slots - they are not good. > >> One thing I've looked at is the way the OR1200 handles the PC, vs. the >> way a pipeline like MIPS does it. The biggest difference between the >> two is that OpenRISC jump offsets are all against the PC, while on >> MIPS the offset is against the PC+4. Doing it either way is fine, but >> it makes me wonder if the OpenRISC uses the non-incremented PC in >> order maybe to avoid a patent held by MIPS. Does anyone know? Perhaps this is just how DLX did it? Not sure why you'd want to do PC+4, either? Perhaps this is just an artifact of something long gone? It shouldn't make much of a different, should it? The only benefit I can think you could get is maybe you save a 32-bit register or a 32-bit adder at some point in your implementation. Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
