On Mon, 2012-04-16 at 16:16 +0200, Peter Gavin wrote:
> Hi guys,
>
> So I've been working on a variation of OpenRISC that doesn't have a
> branch delay slot.
Hi Pete,
Branch delays are definitely out of fashion. RISC-1 introduced them, but
we now know how to avoid them in hardware. Your variant would strictly
speaking not meet the OpenRISC 1000 architecture definition (it mandates
branch delay). Perhaps the architecture spec should be updated to make
branch delay optional.
> One thing I've looked at is the way the OR1200 handles the PC, vs. the
> way a pipeline like MIPS does it. The biggest difference between the
> two is that OpenRISC jump offsets are all against the PC, while on
> MIPS the offset is against the PC+4. Doing it either way is fine, but
> it makes me wonder if the OpenRISC uses the non-incremented PC in
> order maybe to avoid a patent held by MIPS. Does anyone know?
I'm not aware of this, but it would be something to ask Damjan Lampret
(not on this list - you'd have to track him down). Marcus Erlandsson
might also know.
Early MIPS stuff is out of patent. See for example:
http://www.cl.cam.ac.uk/teaching/0910/ECAD+Arch/mips.html
HTH,
Jeremy
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