> Request (1): reset-value of all the bits in this register should come from > some config-pins, which are sampled just at next edge of reset de-assertion > [...]
> Request (2): these bits should be just once-writable after Power-On-Reset. Personally, I would like to have a simple, bug-free, easy-to-use, FPGA-friendly core. I can't see the value of such special features for the general user. In my view, they would add unnecessary complication and yet more cases to test. > I personally would not want users to hack the RTL much, because it > becomes difficult to maintain it as separate branch. If someone needs that kind of advanced features, my guess is that he'll be branching anyway. Regards, rdiez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
