On Tue, May 15, 2012 at 1:37 PM, R. Diez <[email protected]> wrote: > Hi OpenRISC gurus: > > I've seen in this mailing list a patch to implement instruction l.lws, which > is missing from the Verilog core. > > It took me a while to realise that this instruction is in fact redundant in > 32-bit processor implementations, as it does exactly the same as l.lwz, which > is implemented in the current core. > > I have already pointed out a similar case with l.extws and l.extwz: they just > copy a register to another one and are therefore redundant, you can use l.ori > in order to achieve that. > > In the case of l.lws and l.lwz, I would drop l.lws from the specification and > rename l.lwz to l.lw for 32-bit implementations, in order to reduce confusion > and duplication. Few people would notice, as l.lws was never implemented in > or1200 to begin with. > > The confusing part comes from the 's' and the 'z' suffixes, which suggest > sign extension or zero extension, but in fact do nothing at all.
I think it's nice that the instructions for loading/extending a word identical between the 32-bit version and an eventual 64-bit version, though. Perhaps if there we added the l.ld (load doubleword) instruction it would make more sense to keep those the way they are. -Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
