Den 15-05-2012 13:37, R. Diez skrev:
Hi OpenRISC gurus:
I've seen in this mailing list a patch to implement instruction l.lws, which is
missing from the Verilog core.
It took me a while to realise that this instruction is in fact redundant in
32-bit processor implementations, as it does exactly the same as l.lwz, which
is implemented in the current core.
I have already pointed out a similar case with l.extws and l.extwz: they just
copy a register to another one and are therefore redundant, you can use l.ori
in order to achieve that.
In the case of l.lws and l.lwz, I would drop l.lws from the specification and
rename l.lwz to l.lw for 32-bit implementations, in order to reduce confusion
and duplication. Few people would notice, as l.lws was never implemented in
or1200 to begin with.
The confusing part comes from the 's' and the 'z' suffixes, which suggest sign
extension or zero extension, but in fact do nothing at all.
Regards,
rdiez
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I think it would make sense to remove it, but it would mean there's less
similarities between the OR32 and OR64 specifications. I ended up in the
same predicament as you, wondering why my words simply weren't loaded :)
And it makes me wonder how many other instructions aren't implemented
and don't generate invalid instruction exceptions.
In case it's not dropped here's a potential patch to add it I made ages
ago: http://j-software.dk/lws-support.patch
Regards,
Jeppe
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